Commit 33de13da authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r9a07g054: Add DSI node 



Add DSI node to RZ/V2L SoC DTSI.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230411100346.299768-7-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 862b676c

arch/arm64/boot/dts/renesas/r9a07g054.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -623,6 +623,34 @@ 
			status = "disabled";

		};



		dsi: dsi@10850000 {

			compatible = "renesas,r9a07g054-mipi-dsi",

				     "renesas,rzg2l-mipi-dsi";

			reg = <0 0x10850000 0 0x20000>;

			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "seq0", "seq1", "vin1", "rcv",

					  "ferr", "ppi", "debug";

			clocks = <&cpg CPG_MOD R9A07G054_MIPI_DSI_PLLCLK>,

				 <&cpg CPG_MOD R9A07G054_MIPI_DSI_SYSCLK>,

				 <&cpg CPG_MOD R9A07G054_MIPI_DSI_ACLK>,

				 <&cpg CPG_MOD R9A07G054_MIPI_DSI_PCLK>,

				 <&cpg CPG_MOD R9A07G054_MIPI_DSI_VCLK>,

				 <&cpg CPG_MOD R9A07G054_MIPI_DSI_LPCLK>;

			clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";

			resets = <&cpg R9A07G054_MIPI_DSI_CMN_RSTB>,

				 <&cpg R9A07G054_MIPI_DSI_ARESET_N>,

				 <&cpg R9A07G054_MIPI_DSI_PRESET_N>;

			reset-names = "rst", "arst", "prst";

			power-domains = <&cpg>;

			status = "disabled";

		};



		vspd: vsp@10870000 {

			compatible = "renesas,r9a07g054-vsp2",

				     "renesas,r9a07g044-vsp2";