Unverified Commit 33c097cb authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!9357 Add support for Hygon model 7h processors 

Merge Pull Request from: @liao-xuan1 
 
Update L3 PMU and NB, EDAC drivers for Hygon family 18h model 7h processors.

Reference:
https://gitee.com/openeuler/kernel/pulls/8831
https://gitee.com/openeuler/kernel/pulls/1638 
 
Link:https://gitee.com/openeuler/kernel/pulls/9357

 

Reviewed-by: default avatarYuan Can <yuancan@huawei.com>
Reviewed-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: default avatarYuan Can <yuancan@huawei.com>
parents c9c0a907 86d76168

arch/x86/events/amd/uncore.c

+4 −2
Original line number Diff line number Diff line
@@ -196,7 +196,8 @@ static u64 l3_thread_slice_mask(u64 config) 


	if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&

	    boot_cpu_data.x86 == 0x18) {

		if (boot_cpu_data.x86_model == 0x6)

		if (boot_cpu_data.x86_model >= 0x6 &&

		    boot_cpu_data.x86_model <= 0xf)

			return ((config & HYGON_L3_SLICE_MASK) ? : HYGON_L3_SLICE_MASK) |

			       ((config & HYGON_L3_THREAD_MASK) ? : HYGON_L3_THREAD_MASK);

		else
@@ -642,7 +643,8 @@ static int __init amd_uncore_init(void) 
			   boot_cpu_data.x86 == 0x18) {

			*l3_attr++ = &format_attr_event8.attr;

			*l3_attr++ = &format_attr_umask.attr;

			if (boot_cpu_data.x86_model == 6) {

			if (boot_cpu_data.x86_model >= 6 &&

			    boot_cpu_data.x86_model <= 0xf) {

				*l3_attr++ = &format_attr_slicemask4.attr;

				*l3_attr++ = &format_attr_threadmask32.attr;

			} else {

arch/x86/kernel/amd_nb.c

+4 −1
Original line number Diff line number Diff line
@@ -281,6 +281,7 @@ static int get_df_register(struct pci_dev *misc, u8 func, int offset, u32 *value 
				device = PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1;

			break;

		case 0x6:

		case 0x7:

			device = PCI_DEVICE_ID_HYGON_18H_M05H_DF_F1;

			break;

		default:
@@ -289,6 +290,7 @@ static int get_df_register(struct pci_dev *misc, u8 func, int offset, u32 *value 
	} else if (func == 5) {

		switch (boot_cpu_data.x86_model) {

		case 0x6:

		case 0x7:

			device = PCI_DEVICE_ID_HYGON_18H_M06H_DF_F5;

			break;

		default:
@@ -321,7 +323,8 @@ int get_df_id(struct pci_dev *misc, u8 *id) 
	u32 value;

	int ret;



	if (boot_cpu_data.x86_model == 0x6) {

	if (boot_cpu_data.x86_model >= 0x6 &&

	    boot_cpu_data.x86_model <= 0x7) {

		/* F5x180[19:16]: DF ID */

		ret = get_df_register(misc, 5, 0x180, &value);

		*id = (value >> 16) & 0xf;

drivers/edac/amd64_edac.c

+5 −0
Original line number Diff line number Diff line
@@ -3568,6 +3568,11 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) 
			fam_type = &family_types[F18_M06H_CPUS];

			pvt->ops = &family_types[F18_M06H_CPUS].ops;

			break;

		} else if (pvt->model == 0x7) {

			fam_type = &family_types[F18_M06H_CPUS];

			pvt->ops = &family_types[F18_M06H_CPUS].ops;

			family_types[F18_M06H_CPUS].ctl_name = "F18h_M07h";

			break;

		} else if (pvt->model == 0x10) {

			fam_type = &family_types[F18_M10H_CPUS];

			pvt->ops = &family_types[F18_M10H_CPUS].ops;