Commit 33b22d9c authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g044: Add TSU clock and reset entry 



Add TSU clock and reset entry to CPG driver.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211120180438.8351-1-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 45177fc6

drivers/clk/renesas/r9a07g044-cpg.c

+3 −0
Original line number Diff line number Diff line
@@ -260,6 +260,8 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 
				0x5a8, 0),

	DEF_MOD("adc_pclk",	R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,

				0x5a8, 1),

	DEF_MOD("tsu_pclk",	R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,

				0x5ac, 0),

};



static struct rzg2l_reset r9a07g044_resets[] = {
@@ -308,6 +310,7 @@ static struct rzg2l_reset r9a07g044_resets[] = { 
	DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),

	DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),

	DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),

	DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),

};



static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {