Commit 33a220f6 authored by Alan Previn's avatar Alan Previn Committed by Lucas De Marchi
Browse files

drm/i915/guc: Add DG2 registers for GuC error state capture. 



Add additional DG2 registers for GuC error state capture.

Signed-off-by: default avatarAlan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: default avatarUmesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220321164527.2500062-5-alan.previn.teres.alexis@intel.com
parent 193be3f4

drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c

+77 −3
Original line number Diff line number Diff line
@@ -285,20 +285,94 @@ guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc *guc, 
	guc->capture->extlists = extlists;

}



static const struct __ext_steer_reg xehpg_extregs[] = {

	{"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG}

};



static bool __has_xehpg_extregs(u32 ipver)

{

	return (ipver >= IP_VER(12, 55));

}



static void

guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,

				       const struct __guc_mmio_reg_descr_group *lists,

				       u32 ipver)

{

	struct intel_gt *gt = guc_to_gt(guc);

	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;

	struct sseu_dev_info *sseu;

	int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0;

	const struct __guc_mmio_reg_descr_group *list;

	struct __guc_mmio_reg_descr_group *extlists;

	struct __guc_mmio_reg_descr *extarray;



	/* In XE_LP / HPG we only have render-class steering registers during error-capture */

	list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF,

					GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS);

	/* skip if extlists was previously allocated */

	if (!list || guc->capture->extlists)

		return;



	num_steer_regs = ARRAY_SIZE(xe_extregs);

	if (__has_xehpg_extregs(ipver))

		num_steer_regs += ARRAY_SIZE(xehpg_extregs);



	sseu = &gt->info.sseu;

	for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) {

		num_tot_regs += num_steer_regs;

	}



	if (!num_tot_regs)

		return;



	/* allocate an extra for an end marker */

	extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL);

	if (!extlists)

		return;



	if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) {

		kfree(extlists);

		return;

	}



	extarray = extlists[0].extlist;

	for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) {

		for (i = 0; i < ARRAY_SIZE(xe_extregs); ++i) {

			__fill_ext_reg(extarray, &xe_extregs[i], slice, subslice);

			++extarray;

		}

		if (__has_xehpg_extregs(ipver)) {

			for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) {

				__fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice);

				++extarray;

			}

		}

	}



	drm_dbg(&i915->drm, "GuC-capture found %d-ext-regs.\n", num_tot_regs);

	guc->capture->extlists = extlists;

}



static const struct __guc_mmio_reg_descr_group *

guc_capture_get_device_reglist(struct intel_guc *guc)

{

	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;



	if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915) ||

	    IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {

	if (GRAPHICS_VER(i915) > 11) {

		/*

		 * For certain engine classes, there are slice and subslice

		 * level registers requiring steering. We allocate and populate

		 * these at init time based on hw config add it as an extension

		 * list at the end of the pre-populated render list.

		 */

		if (IS_DG2(i915))

			guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 55));

		else if (IS_XEHPSDV(i915))

			guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 50));

		else

			guc_capture_alloc_steered_lists_xe_lpd(guc, xe_lpd_lists);



		return xe_lpd_lists;

	}