Commit 33936499 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2020-08-24-1' of... 

Merge tag 'drm-intel-next-2020-08-24-1' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

UAPI Changes:

- Introduce a mechanism to extend execbuf2 (Lionel)
- Add syncobj timeline support (Lionel)

Driver Changes:

- Limit stolen mem usage on the compressed frame buffer (Ville)
- Some clean-up around display's cdclk (Ville)
- Some DDI changes for better DP link training according
  to spec (Imre)
- Provide the perf pmu.module (Chris)
- Remove dobious Valleyview PCI IDs (Alexei)
- Add new display power saving feature for gen12+ called
  HOBL (Jose)
- Move SKL's clock gating w/a to skl_init_clock_gating() (Ville)
- Rocket Lake display additions (Matt)
- Selftest: temporarily downgrade on severity of frequency
            scaling tests (Chris)
- Introduce a new display workaround for fixing FLR related
  issues on new PCH. (Jose)
- Temporarily disable FBC on TGL. It was the culprit of random
  underruns. (Uma).
- Copy default modparams to mock i915_device (Chris)
- Add compiler paranoia for checking HWSP values (Chris)
- Remove useless gen check before calling intel_rps_boost (Chris)
- Fix a null pointer dereference (Chris)
- Add a couple of missing i915_active_fini() (Chris)
- Update TGL display power's bw_buddy table according to
  update spec (Matt)
- Fix couple wrong return values (Tianjia)
- Selftest: Avoid passing random 0 into ilog2 (George)
- Many Tiger Lake display fixes and improvements for Type-C and
  DP compliance (Imre, Jose)
- Start the addition of PSR2 selective fetch (Jose)
- Update a few DMC and HuC firmware versions (Jose)
- Add gen11+ w/a to fix underuns (Matt)
- Fix cmd parser desc matching with mask (Mika)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200826232733.GA129053@intel.com
parents cbc2e829 ced026e9

drivers/gpu/drm/i915/display/intel_cdclk.c

+6 −5
Original line number Diff line number Diff line
@@ -2903,9 +2903,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
		dev_priv->display.get_cdclk = i85x_get_cdclk;

	else if (IS_I845G(dev_priv))

		dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;

	else { /* 830 */

		drm_WARN(&dev_priv->drm, !IS_I830(dev_priv),

			 "Unknown platform. Assuming 133 MHz CDCLK\n");

	else if (IS_I830(dev_priv))

		dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;



	if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk,

		     "Unknown platform. Assuming 133 MHz CDCLK\n"))

		dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;

	}

}

drivers/gpu/drm/i915/display/intel_cdclk.h

+1 −1
Original line number Diff line number Diff line
@@ -17,8 +17,8 @@ struct intel_atomic_state; 
struct intel_crtc_state;



struct intel_cdclk_vals {

	u16 refclk;

	u32 cdclk;

	u16 refclk;

	u8 divider;	/* CD2X divider * 2 */

	u8 ratio;

};

drivers/gpu/drm/i915/display/intel_csr.c

+4 −4
Original line number Diff line number Diff line
@@ -40,12 +40,12 @@ 


#define GEN12_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE



#define RKL_CSR_PATH			"i915/rkl_dmc_ver2_01.bin"

#define RKL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 1)

#define RKL_CSR_PATH			"i915/rkl_dmc_ver2_02.bin"

#define RKL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 2)

MODULE_FIRMWARE(RKL_CSR_PATH);



#define TGL_CSR_PATH			"i915/tgl_dmc_ver2_06.bin"

#define TGL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 6)

#define TGL_CSR_PATH			"i915/tgl_dmc_ver2_08.bin"

#define TGL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 8)

#define TGL_CSR_MAX_FW_SIZE		0x6000

MODULE_FIRMWARE(TGL_CSR_PATH);

drivers/gpu/drm/i915/display/intel_ddi.c

+97 −14
Original line number Diff line number Diff line
@@ -706,6 +706,42 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = 
	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */

};



static const struct cnl_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = {

						/* NT mV Trans mV db    */

	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */

	{ 0xA, 0x4F, 0x36, 0x00, 0x09 },	/* 350   500      3.1   */

	{ 0xC, 0x60, 0x32, 0x00, 0x0D },	/* 350   700      6.0   */

	{ 0xC, 0x7F, 0x2D, 0x00, 0x12 },	/* 350   900      8.2   */

	{ 0xC, 0x47, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */

	{ 0xC, 0x6F, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */

	{ 0x6, 0x7D, 0x32, 0x00, 0x0D },	/* 500   900      5.1   */

	{ 0x6, 0x60, 0x3C, 0x00, 0x03 },	/* 650   700      0.6   */

	{ 0x6, 0x7F, 0x34, 0x00, 0x0B },	/* 600   900      3.5   */

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */

};



/*

 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries

 * that DisplayPort specification requires

 */

static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {

						/* VS	pre-emp	*/

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 0	0	*/

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 0	1	*/

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 0	2	*/

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 0	3	*/

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1	0	*/

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1	1	*/

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1	2	*/

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 2	0	*/

	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 2	1	*/

};



static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)

{

	return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;

}



static const struct ddi_buf_trans *

bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)

{
@@ -1050,9 +1086,26 @@ static const struct cnl_ddi_buf_trans * 
tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,

			int *n_entries)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.hobl) {

		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);



		if (!intel_dp->hobl_failed && rate <= 540000) {

			/* Same table applies to TGL, RKL and DG1 */

			*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);

			return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;

		}

	}



	if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) {

		return icl_get_combo_buf_trans(encoder, type, rate, n_entries);

	} else if (rate > 270000) {

		if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {

			*n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);

			return tgl_uy_combo_phy_ddi_translations_dp_hbr2;

		}



		*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);

		return tgl_combo_phy_ddi_translations_dp_hbr2;

	}
@@ -2392,6 +2445,15 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 
		level = n_entries - 1;

	}



	if (type == INTEL_OUTPUT_EDP) {

		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);



		val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;

		intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);

		intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,

			     intel_dp->hobl_active ? val : 0);

	}



	/* Set PORT_TX_DW5 */

	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));

	val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
@@ -2802,7 +2864,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp) 
static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,

				     enum phy phy)

{

	if (intel_phy_is_combo(dev_priv, phy)) {

	if (IS_ROCKETLAKE(dev_priv)) {

		return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);

	} else if (intel_phy_is_combo(dev_priv, phy)) {

		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);

	} else if (intel_phy_is_tc(dev_priv, phy)) {

		enum tc_port tc_port = intel_port_to_tc(dev_priv,
@@ -2829,6 +2893,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, 
		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);



	if (intel_phy_is_combo(dev_priv, phy)) {

		u32 mask, sel;



		if (IS_ROCKETLAKE(dev_priv)) {

			mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);

			sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);

		} else {

			mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);

			sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);

		}



		/*

		 * Even though this register references DDIs, note that we

		 * want to pass the PHY rather than the port (DDI).  For
@@ -2839,8 +2913,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, 
		 *   Clock Select chooses the PLL for both DDIA and DDID and

		 *   drives port A in all cases."

		 */

		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);

		val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);

		val &= ~mask;

		val |= sel;

		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);

		intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);

	}
@@ -4037,8 +4111,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 
			intel_wait_ddi_buf_idle(dev_priv, port);

	}



	dp_tp_ctl = DP_TP_CTL_ENABLE |

		    DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;

	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;

	if (intel_dp->link_mst)

		dp_tp_ctl |= DP_TP_CTL_MODE_MST;

	else {
@@ -4061,16 +4134,10 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 
{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);

	enum port port = dp_to_dig_port(intel_dp)->base.port;

	u32 temp;



	temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);



	if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)

		temp |= DP_TP_CTL_SCRAMBLE_DISABLE;

	else

		temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;



	temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;

	switch (dp_train_pat & train_pat_mask) {

	case DP_TRAINING_PATTERN_DISABLE:
@@ -4091,9 +4158,6 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 
	}



	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);



	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);

	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));

}



static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
@@ -4878,6 +4942,13 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port) 
	return max_lanes;

}



static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)

{

	return i915->hti_state & HDPORT_ENABLED &&

		(i915->hti_state & HDPORT_PHY_USED_DP(phy) ||

		 i915->hti_state & HDPORT_PHY_USED_HDMI(phy));

}



void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)

{

	struct intel_digital_port *dig_port;
@@ -4885,6 +4956,18 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 
	bool init_hdmi, init_dp, init_lspcon = false;

	enum phy phy = intel_port_to_phy(dev_priv, port);



	/*

	 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may

	 * have taken over some of the PHYs and made them unavailable to the

	 * driver.  In that case we should skip initializing the corresponding

	 * outputs.

	 */

	if (hti_uses_phy(dev_priv, phy)) {

		drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",

			    port_name(port), phy_name(phy));

		return;

	}



	init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) ||

		intel_bios_port_supports_hdmi(dev_priv, port);

	init_dp = intel_bios_port_supports_dp(dev_priv, port);

drivers/gpu/drm/i915/display/intel_display.c

+75 −13
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ 
#include "display/intel_ddi.h"

#include "display/intel_dp.h"

#include "display/intel_dp_mst.h"

#include "display/intel_dpll_mgr.h"

#include "display/intel_dsi.h"

#include "display/intel_dvo.h"

#include "display/intel_gmbus.h"
@@ -3761,6 +3762,44 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb, 
	}

}









static int icl_min_plane_width(const struct drm_framebuffer *fb)









{









	/* Wa_14011264657, Wa_14011050563: gen11+ */









	switch (fb->format->format) {









	case DRM_FORMAT_C8:









		return 18;









	case DRM_FORMAT_RGB565:









		return 10;









	case DRM_FORMAT_XRGB8888:









	case DRM_FORMAT_XBGR8888:









	case DRM_FORMAT_ARGB8888:









	case DRM_FORMAT_ABGR8888:









	case DRM_FORMAT_XRGB2101010:









	case DRM_FORMAT_XBGR2101010:









	case DRM_FORMAT_ARGB2101010:









	case DRM_FORMAT_ABGR2101010:









	case DRM_FORMAT_XVYU2101010:









	case DRM_FORMAT_Y212:









	case DRM_FORMAT_Y216:









		return 6;









	case DRM_FORMAT_NV12:









		return 20;









	case DRM_FORMAT_P010:









	case DRM_FORMAT_P012:









	case DRM_FORMAT_P016:









		return 12;









	case DRM_FORMAT_XRGB16161616F:









	case DRM_FORMAT_XBGR16161616F:









	case DRM_FORMAT_ARGB16161616F:









	case DRM_FORMAT_ABGR16161616F:









	case DRM_FORMAT_XVYU12_16161616:









	case DRM_FORMAT_XVYU16161616:









		return 4;









	default:









		return 1;









	}









}

















static int icl_max_plane_width(const struct drm_framebuffer *fb,









			       int color_plane,









			       unsigned int rotation)








@@ -3843,29 +3882,31 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)







	int y = plane_state->uapi.src.y1 >> 16;









	int w = drm_rect_width(&plane_state->uapi.src) >> 16;









	int h = drm_rect_height(&plane_state->uapi.src) >> 16;









	int max_width;









	int max_height;









	u32 alignment;









	u32 offset;









	int max_width, min_width, max_height;









	u32 alignment, offset;









	int aux_plane = intel_main_to_aux_plane(fb, 0);









	u32 aux_offset = plane_state->color_plane[aux_plane].offset;

















	if (INTEL_GEN(dev_priv) >= 11)









	if (INTEL_GEN(dev_priv) >= 11) {









		max_width = icl_max_plane_width(fb, 0, rotation);









	else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))









		min_width = icl_min_plane_width(fb);









	} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {









		max_width = glk_max_plane_width(fb, 0, rotation);









	else









		min_width = 1;









	} else {









		max_width = skl_max_plane_width(fb, 0, rotation);









		min_width = 1;









	}

















	if (INTEL_GEN(dev_priv) >= 11)









		max_height = icl_max_plane_height();









	else









		max_height = skl_max_plane_height();

















	if (w > max_width || h > max_height) {









	if (w > max_width || w < min_width || h > max_height) {









		drm_dbg_kms(&dev_priv->drm,









			    "requested Y/RGB source size %dx%d too big (limit %dx%d)\n",









			    w, h, max_width, max_height);









			    "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",









			    w, h, min_width, max_width, max_height);









		return -EINVAL;









	}
















@@ -10802,9 +10843,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,







	u32 temp;

















	if (intel_phy_is_combo(dev_priv, phy)) {









		temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) &









			ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);









		id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);









		u32 mask, shift;

















		if (IS_ROCKETLAKE(dev_priv)) {









			mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);









			shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);









		} else {









			mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);









			shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);









		}

















		temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;









		id = temp >> shift;









		port_dpll_id = ICL_PORT_DPLL_DEFAULT;









	} else if (intel_phy_is_tc(dev_priv, phy)) {









		u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;








@@ -12760,6 +12810,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,















	}

















	if (!mode_changed)









		intel_psr2_sel_fetch_update(state, crtc);

















	return 0;









}
















@@ -15136,6 +15189,8 @@ static void commit_pipe_config(struct intel_atomic_state *state,















		if (new_crtc_state->update_pipe)









			intel_pipe_fastset(old_crtc_state, new_crtc_state);

















		intel_psr2_program_trans_man_trk_ctl(new_crtc_state);









	}

















	if (dev_priv->display.atomic_update_watermarks)








@@ -17894,6 +17949,13 @@ int intel_modeset_init(struct drm_i915_private *i915)







	if (i915->max_cdclk_freq == 0)









		intel_update_max_cdclk(i915);

















	/*









	 * If the platform has HTI, we need to find out whether it has reserved









	 * any display resources before we create our display outputs.









	 */









	if (INTEL_INFO(i915)->display.has_hti)









		i915->hti_state = intel_de_read(i915, HDPORT_STATE);

















	/* Just disable it once at startup */









	intel_vga_disable(i915);









	intel_setup_outputs(i915);