Commit 33887fce authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Rob Herring
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dt-bindings: intel,ixp4xx-expansion-bus: split out peripheral properties 



The properties of devices in IXP4xx expansion bus need to be also
applied to actual devices' bindings.  Prepare for this by splitting them
to separate intel,ixp4xx-expansion-peripheral-props binding, just like
other memory-controller peripheral properties.

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Acked-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lore.kernel.org/r/20230206092624.22922-2-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent f9b8556d

Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml→Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml

+2 −64
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#

$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel IXP4xx Expansion Bus Controller
@@ -56,69 +56,7 @@ patternProperties: 
    description: Devices attached to chip selects are represented as

      subnodes.

    type: object



    properties:

      intel,ixp4xx-eb-t1:

        description: Address timing, extend address phase with n cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        maximum: 3



      intel,ixp4xx-eb-t2:

        description: Setup chip select timing, extend setup phase with n cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        maximum: 3



      intel,ixp4xx-eb-t3:

        description: Strobe timing, extend strobe phase with n cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        maximum: 15



      intel,ixp4xx-eb-t4:

        description: Hold timing, extend hold phase with n cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        maximum: 3



      intel,ixp4xx-eb-t5:

        description: Recovery timing, extend recovery phase with n cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        maximum: 15



      intel,ixp4xx-eb-cycle-type:

        description: The type of cycles to use on the expansion bus for this

          chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1, 2]



      intel,ixp4xx-eb-byte-access-on-halfword:

        description: Allow byte read access on half word devices.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1]



      intel,ixp4xx-eb-hpi-hrdy-pol-high:

        description: Set HPI HRDY polarity to active high when using HPI.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1]



      intel,ixp4xx-eb-mux-address-and-data:

        description: Multiplex address and data on the data bus.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1]



      intel,ixp4xx-eb-ahb-split-transfers:

        description: Enable AHB split transfers.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1]



      intel,ixp4xx-eb-write-enable:

        description: Enable write cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1]



      intel,ixp4xx-eb-byte-access:

        description: Expansion bus uses only 8 bits. The default is to use

          16 bits.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1]

    $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#



required:

  - compatible

Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml

0 → 100644
+80 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Peripheral properties for Intel IXP4xx Expansion Bus



description:

  The IXP4xx expansion bus controller handles access to devices on the

  memory-mapped expansion bus on the Intel IXP4xx family of system on chips,

  including IXP42x, IXP43x, IXP45x and IXP46x.



maintainers:

  - Linus Walleij <linus.walleij@linaro.org>



properties:

  intel,ixp4xx-eb-t1:

    description: Address timing, extend address phase with n cycles.

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 3



  intel,ixp4xx-eb-t2:

    description: Setup chip select timing, extend setup phase with n cycles.

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 3



  intel,ixp4xx-eb-t3:

    description: Strobe timing, extend strobe phase with n cycles.

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15



  intel,ixp4xx-eb-t4:

    description: Hold timing, extend hold phase with n cycles.

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 3



  intel,ixp4xx-eb-t5:

    description: Recovery timing, extend recovery phase with n cycles.

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 15



  intel,ixp4xx-eb-cycle-type:

    description: The type of cycles to use on the expansion bus for this

      chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1, 2]



  intel,ixp4xx-eb-byte-access-on-halfword:

    description: Allow byte read access on half word devices.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1]



  intel,ixp4xx-eb-hpi-hrdy-pol-high:

    description: Set HPI HRDY polarity to active high when using HPI.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1]



  intel,ixp4xx-eb-mux-address-and-data:

    description: Multiplex address and data on the data bus.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1]



  intel,ixp4xx-eb-ahb-split-transfers:

    description: Enable AHB split transfers.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1]



  intel,ixp4xx-eb-write-enable:

    description: Enable write cycles.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1]



  intel,ixp4xx-eb-byte-access:

    description: Expansion bus uses only 8 bits. The default is to use

      16 bits.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1]



additionalProperties: true

Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml

+1 −0
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@@ -34,5 +34,6 @@ required: 
# The controller specific properties go here.

allOf:

  - $ref: st,stm32-fmc2-ebi-props.yaml#

  - $ref: intel,ixp4xx-expansion-peripheral-props.yaml#



additionalProperties: true

MAINTAINERS

+1 −1
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@@ -2326,7 +2326,7 @@ M: Krzysztof Halasa <khalasa@piap.pl> 
L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml

F:	Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml

F:	Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion*

F:	Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt

F:	Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml

F:	Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml