Commit 3356c38d authored by Graham Sider's avatar Graham Sider Committed by Alex Deucher
Browse files

drm/amdkfd: replace kgd_dev in various kfd2kgd funcs 



Modified definitions:

- program_sh_mem_settings
- set_pasid_vmid_mapping
- init_interrupts
- address_watch_disable
- address_watch_execute
- wave_control_execute
- address_watch_get_offset
- get_atc_vmid_pasid_mapping_info
- set_scratch_backing_va
- set_vm_context_page_table_base
- read_vmid_from_vmfault_reg
- get_cu_occupancy
- program_trap_handler_settings

Signed-off-by: default avatarGraham Sider <Graham.Sider@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 420185fd

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

+11 −22
Original line number Diff line number Diff line
@@ -80,14 +80,12 @@ static void release_queue(struct amdgpu_device *adev) 
	unlock_srbm(adev);

}



static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,

static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,

					uint32_t sh_mem_config,

					uint32_t sh_mem_ape1_base,

					uint32_t sh_mem_ape1_limit,

					uint32_t sh_mem_bases)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	lock_srbm(adev, 0, 0, 0, vmid);



	WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
@@ -97,11 +95,9 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 
	unlock_srbm(adev);

}



static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid,

static int kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,

					unsigned int vmid)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	/*

	 * We have to assume that there is no outstanding mapping.

	 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
@@ -144,9 +140,8 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid, 
 * but still works

 */



static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)

static int kgd_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t mec;

	uint32_t pipe;
@@ -669,11 +664,10 @@ static int kgd_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd, 
	return 0;

}



static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,

static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,

					uint8_t vmid, uint16_t *p_pasid)

{

	uint32_t value;

	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;



	value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)

		     + vmid);
@@ -682,12 +676,12 @@ static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd, 
	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);

}



static int kgd_address_watch_disable(struct kgd_dev *kgd)

static int kgd_address_watch_disable(struct amdgpu_device *adev)

{

	return 0;

}



static int kgd_address_watch_execute(struct kgd_dev *kgd,

static int kgd_address_watch_execute(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					uint32_t cntl_val,

					uint32_t addr_hi,
@@ -696,11 +690,10 @@ static int kgd_address_watch_execute(struct kgd_dev *kgd, 
	return 0;

}



static int kgd_wave_control_execute(struct kgd_dev *kgd,

static int kgd_wave_control_execute(struct amdgpu_device *adev,

					uint32_t gfx_index_val,

					uint32_t sq_cmd)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t data = 0;



	mutex_lock(&adev->grbm_idx_mutex);
@@ -721,18 +714,16 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd, 
	return 0;

}



static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,

static uint32_t kgd_address_watch_get_offset(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					unsigned int reg_offset)

{

	return 0;

}



static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,

		uint64_t page_table_base)

static void set_vm_context_page_table_base(struct amdgpu_device *adev,

		uint32_t vmid, uint64_t page_table_base)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {

		pr_err("trying to set page table base for wrong VMID %u\n",

		       vmid);
@@ -743,11 +734,9 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 
	adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);

}



static void program_trap_handler_settings(struct kgd_dev *kgd,

static void program_trap_handler_settings(struct amdgpu_device *adev,

		uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	lock_srbm(adev, 0, 0, 0, vmid);



	/*

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

+16 −33
Original line number Diff line number Diff line
@@ -79,14 +79,12 @@ static void release_queue(struct amdgpu_device *adev) 
	unlock_srbm(adev);

}



static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid,

static void program_sh_mem_settings_v10_3(struct amdgpu_device *adev, uint32_t vmid,

					uint32_t sh_mem_config,

					uint32_t sh_mem_ape1_base,

					uint32_t sh_mem_ape1_limit,

					uint32_t sh_mem_bases)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	lock_srbm(adev, 0, 0, 0, vmid);



	WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
@@ -97,11 +95,9 @@ static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid, 
}



/* ATC is defeatured on Sienna_Cichlid */

static int set_pasid_vmid_mapping_v10_3(struct kgd_dev *kgd, unsigned int pasid,

static int set_pasid_vmid_mapping_v10_3(struct amdgpu_device *adev, unsigned int pasid,

					unsigned int vmid)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	uint32_t value = pasid << IH_VMID_0_LUT__PASID__SHIFT;



	/* Mapping vmid to pasid also for IH block */
@@ -112,9 +108,8 @@ static int set_pasid_vmid_mapping_v10_3(struct kgd_dev *kgd, unsigned int pasid, 
	return 0;

}



static int init_interrupts_v10_3(struct kgd_dev *kgd, uint32_t pipe_id)

static int init_interrupts_v10_3(struct amdgpu_device *adev, uint32_t pipe_id)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t mec;

	uint32_t pipe;
@@ -593,12 +588,12 @@ static int hqd_sdma_destroy_v10_3(struct amdgpu_device *adev, void *mqd, 
}





static int address_watch_disable_v10_3(struct kgd_dev *kgd)

static int address_watch_disable_v10_3(struct amdgpu_device *adev)

{

	return 0;

}



static int address_watch_execute_v10_3(struct kgd_dev *kgd,

static int address_watch_execute_v10_3(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					uint32_t cntl_val,

					uint32_t addr_hi,
@@ -607,11 +602,10 @@ static int address_watch_execute_v10_3(struct kgd_dev *kgd, 
	return 0;

}



static int wave_control_execute_v10_3(struct kgd_dev *kgd,

static int wave_control_execute_v10_3(struct amdgpu_device *adev,

					uint32_t gfx_index_val,

					uint32_t sq_cmd)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t data = 0;



	mutex_lock(&adev->grbm_idx_mutex);
@@ -632,27 +626,23 @@ static int wave_control_execute_v10_3(struct kgd_dev *kgd, 
	return 0;

}



static uint32_t address_watch_get_offset_v10_3(struct kgd_dev *kgd,

static uint32_t address_watch_get_offset_v10_3(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					unsigned int reg_offset)

{

	return 0;

}



static void set_vm_context_page_table_base_v10_3(struct kgd_dev *kgd, uint32_t vmid,

		uint64_t page_table_base)

static void set_vm_context_page_table_base_v10_3(struct amdgpu_device *adev,

		uint32_t vmid, uint64_t page_table_base)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	/* SDMA is on gfxhub as well for Navi1* series */

	adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);

}



static void program_trap_handler_settings_v10_3(struct kgd_dev *kgd,

static void program_trap_handler_settings_v10_3(struct amdgpu_device *adev,

			uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	lock_srbm(adev, 0, 0, 0, vmid);



	/*
@@ -676,11 +666,10 @@ static void program_trap_handler_settings_v10_3(struct kgd_dev *kgd, 
}



#if 0

uint32_t enable_debug_trap_v10_3(struct kgd_dev *kgd,

uint32_t enable_debug_trap_v10_3(struct amdgpu_device *adev,

				uint32_t trap_debug_wave_launch_mode,

				uint32_t vmid)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t data = 0;

	uint32_t orig_wave_cntl_value;

	uint32_t orig_stall_vmid;
@@ -707,10 +696,8 @@ uint32_t enable_debug_trap_v10_3(struct kgd_dev *kgd, 
	return 0;

}



uint32_t disable_debug_trap_v10_3(struct kgd_dev *kgd)

uint32_t disable_debug_trap_v10_3(struct amdgpu_device *adev)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	mutex_lock(&adev->grbm_idx_mutex);



	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
@@ -720,11 +707,10 @@ uint32_t disable_debug_trap_v10_3(struct kgd_dev *kgd) 
	return 0;

}



uint32_t set_wave_launch_trap_override_v10_3(struct kgd_dev *kgd,

uint32_t set_wave_launch_trap_override_v10_3(struct amdgpu_device *adev,

						uint32_t trap_override,

						uint32_t trap_mask)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t data = 0;



	mutex_lock(&adev->grbm_idx_mutex);
@@ -749,11 +735,10 @@ uint32_t set_wave_launch_trap_override_v10_3(struct kgd_dev *kgd, 
	return 0;

}



uint32_t set_wave_launch_mode_v10_3(struct kgd_dev *kgd,

uint32_t set_wave_launch_mode_v10_3(struct amdgpu_device *adev,

					uint8_t wave_launch_mode,

					uint32_t vmid)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t data = 0;

	bool is_stall_mode;

	bool is_mode_set;
@@ -792,16 +777,14 @@ uint32_t set_wave_launch_mode_v10_3(struct kgd_dev *kgd, 
 *	sem_rearm_wait_time      -- Wait Count for Semaphore re-arm.

 *	deq_retry_wait_time      -- Wait Count for Global Wave Syncs.

 */

void get_iq_wait_times_v10_3(struct kgd_dev *kgd,

void get_iq_wait_times_v10_3(struct amdgpu_device *adev,

					uint32_t *wait_times)



{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	*wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));

}



void build_grace_period_packet_info_v10_3(struct kgd_dev *kgd,

void build_grace_period_packet_info_v10_3(struct amdgpu_device *adev,

						uint32_t wait_times,

						uint32_t grace_period,

						uint32_t *reg_offset,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

+12 −27
Original line number Diff line number Diff line
@@ -116,14 +116,12 @@ static void release_queue(struct amdgpu_device *adev) 
	unlock_srbm(adev);

}



static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,

static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,

					uint32_t sh_mem_config,

					uint32_t sh_mem_ape1_base,

					uint32_t sh_mem_ape1_limit,

					uint32_t sh_mem_bases)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	lock_srbm(adev, 0, 0, 0, vmid);



	WREG32(mmSH_MEM_CONFIG, sh_mem_config);
@@ -134,11 +132,9 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 
	unlock_srbm(adev);

}



static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid,

static int kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,

					unsigned int vmid)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	/*

	 * We have to assume that there is no outstanding mapping.

	 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
@@ -160,9 +156,8 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid, 
	return 0;

}



static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)

static int kgd_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t mec;

	uint32_t pipe;
@@ -539,9 +534,8 @@ static int kgd_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd, 
	return 0;

}



static int kgd_address_watch_disable(struct kgd_dev *kgd)

static int kgd_address_watch_disable(struct amdgpu_device *adev)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	union TCP_WATCH_CNTL_BITS cntl;

	unsigned int i;
@@ -559,13 +553,12 @@ static int kgd_address_watch_disable(struct kgd_dev *kgd) 
	return 0;

}



static int kgd_address_watch_execute(struct kgd_dev *kgd,

static int kgd_address_watch_execute(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					uint32_t cntl_val,

					uint32_t addr_hi,

					uint32_t addr_lo)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	union TCP_WATCH_CNTL_BITS cntl;



	cntl.u32All = cntl_val;
@@ -590,11 +583,10 @@ static int kgd_address_watch_execute(struct kgd_dev *kgd, 
	return 0;

}



static int kgd_wave_control_execute(struct kgd_dev *kgd,

static int kgd_wave_control_execute(struct amdgpu_device *adev,

					uint32_t gfx_index_val,

					uint32_t sq_cmd)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t data;



	mutex_lock(&adev->grbm_idx_mutex);
@@ -615,18 +607,17 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd, 
	return 0;

}



static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,

static uint32_t kgd_address_watch_get_offset(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					unsigned int reg_offset)

{

	return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];

}



static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,

static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,

					uint8_t vmid, uint16_t *p_pasid)

{

	uint32_t value;

	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;



	value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);

	*p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
@@ -634,21 +625,17 @@ static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd, 
	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);

}



static void set_scratch_backing_va(struct kgd_dev *kgd,

static void set_scratch_backing_va(struct amdgpu_device *adev,

					uint64_t va, uint32_t vmid)

{

	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;



	lock_srbm(adev, 0, 0, 0, vmid);

	WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);

	unlock_srbm(adev);

}



static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,

			uint64_t page_table_base)

static void set_vm_context_page_table_base(struct amdgpu_device *adev,

			uint32_t vmid, uint64_t page_table_base)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {

		pr_err("trying to set page table base for wrong VMID\n");

		return;
@@ -664,10 +651,8 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 
  * @vmid: vmid pointer

  * read vmid from register (CIK).

  */

static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd)

static uint32_t read_vmid_from_vmfault_reg(struct amdgpu_device *adev)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);



	return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

+11 −22
Original line number Diff line number Diff line
@@ -73,14 +73,12 @@ static void release_queue(struct amdgpu_device *adev) 
	unlock_srbm(adev);

}



static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,

static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,

					uint32_t sh_mem_config,

					uint32_t sh_mem_ape1_base,

					uint32_t sh_mem_ape1_limit,

					uint32_t sh_mem_bases)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	lock_srbm(adev, 0, 0, 0, vmid);



	WREG32(mmSH_MEM_CONFIG, sh_mem_config);
@@ -91,11 +89,9 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 
	unlock_srbm(adev);

}



static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid,

static int kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,

					unsigned int vmid)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	/*

	 * We have to assume that there is no outstanding mapping.

	 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
@@ -118,9 +114,8 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid, 
	return 0;

}



static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)

static int kgd_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t mec;

	uint32_t pipe;
@@ -537,11 +532,10 @@ static int kgd_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd, 
	return 0;

}



static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,

static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,

					uint8_t vmid, uint16_t *p_pasid)

{

	uint32_t value;

	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;



	value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);

	*p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
@@ -549,12 +543,12 @@ static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd, 
	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);

}



static int kgd_address_watch_disable(struct kgd_dev *kgd)

static int kgd_address_watch_disable(struct amdgpu_device *adev)

{

	return 0;

}



static int kgd_address_watch_execute(struct kgd_dev *kgd,

static int kgd_address_watch_execute(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					uint32_t cntl_val,

					uint32_t addr_hi,
@@ -563,11 +557,10 @@ static int kgd_address_watch_execute(struct kgd_dev *kgd, 
	return 0;

}



static int kgd_wave_control_execute(struct kgd_dev *kgd,

static int kgd_wave_control_execute(struct amdgpu_device *adev,

					uint32_t gfx_index_val,

					uint32_t sq_cmd)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t data = 0;



	mutex_lock(&adev->grbm_idx_mutex);
@@ -588,28 +581,24 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd, 
	return 0;

}



static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,

static uint32_t kgd_address_watch_get_offset(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					unsigned int reg_offset)

{

	return 0;

}



static void set_scratch_backing_va(struct kgd_dev *kgd,

static void set_scratch_backing_va(struct amdgpu_device *adev,

					uint64_t va, uint32_t vmid)

{

	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;



	lock_srbm(adev, 0, 0, 0, vmid);

	WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);

	unlock_srbm(adev);

}



static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,

		uint64_t page_table_base)

static void set_vm_context_page_table_base(struct amdgpu_device *adev,

		uint32_t vmid, uint64_t page_table_base)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {

		pr_err("trying to set page table base for wrong VMID\n");

		return;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

+11 −24
Original line number Diff line number Diff line
@@ -87,14 +87,12 @@ static void release_queue(struct amdgpu_device *adev) 
	unlock_srbm(adev);

}



void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,

void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,

					uint32_t sh_mem_config,

					uint32_t sh_mem_ape1_base,

					uint32_t sh_mem_ape1_limit,

					uint32_t sh_mem_bases)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	lock_srbm(adev, 0, 0, 0, vmid);



	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
@@ -104,11 +102,9 @@ void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 
	unlock_srbm(adev);

}



int kgd_gfx_v9_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid,

int kgd_gfx_v9_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,

					unsigned int vmid)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	/*

	 * We have to assume that there is no outstanding mapping.

	 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
@@ -165,9 +161,8 @@ int kgd_gfx_v9_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid, 
 * but still works

 */



int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)

int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t mec;

	uint32_t pipe;
@@ -620,11 +615,10 @@ static int kgd_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd, 
	return 0;

}



bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,

bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,

					uint8_t vmid, uint16_t *p_pasid)

{

	uint32_t value;

	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;



	value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)

		     + vmid);
@@ -633,12 +627,12 @@ bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd, 
	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);

}



int kgd_gfx_v9_address_watch_disable(struct kgd_dev *kgd)

int kgd_gfx_v9_address_watch_disable(struct amdgpu_device *adev)

{

	return 0;

}



int kgd_gfx_v9_address_watch_execute(struct kgd_dev *kgd,

int kgd_gfx_v9_address_watch_execute(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					uint32_t cntl_val,

					uint32_t addr_hi,
@@ -647,11 +641,10 @@ int kgd_gfx_v9_address_watch_execute(struct kgd_dev *kgd, 
	return 0;

}



int kgd_gfx_v9_wave_control_execute(struct kgd_dev *kgd,

int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev,

					uint32_t gfx_index_val,

					uint32_t sq_cmd)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);

	uint32_t data = 0;



	mutex_lock(&adev->grbm_idx_mutex);
@@ -672,18 +665,16 @@ int kgd_gfx_v9_wave_control_execute(struct kgd_dev *kgd, 
	return 0;

}



uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd,

uint32_t kgd_gfx_v9_address_watch_get_offset(struct amdgpu_device *adev,

					unsigned int watch_point_id,

					unsigned int reg_offset)

{

	return 0;

}



void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd,

void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev,

			uint32_t vmid, uint64_t page_table_base)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {

		pr_err("trying to set page table base for wrong VMID %u\n",

		       vmid);
@@ -790,7 +781,7 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx, 
 *

 *  Reading registers referenced above involves programming GRBM appropriately

 */

void kgd_gfx_v9_get_cu_occupancy(struct kgd_dev *kgd, int pasid,

void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,

		int *pasid_wave_cnt, int *max_waves_per_cu)

{

	int qidx;
@@ -804,10 +795,8 @@ void kgd_gfx_v9_get_cu_occupancy(struct kgd_dev *kgd, int pasid, 
	int pasid_tmp;

	int max_queue_cnt;

	int vmid_wave_cnt = 0;

	struct amdgpu_device *adev;

	DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES);



	adev = get_amdgpu_device(kgd);

	lock_spi_csq_mutexes(adev);

	soc15_grbm_select(adev, 1, 0, 0, 0);
@@ -868,11 +857,9 @@ void kgd_gfx_v9_get_cu_occupancy(struct kgd_dev *kgd, int pasid, 
				adev->gfx.cu_info.max_waves_per_simd;

}



void kgd_gfx_v9_program_trap_handler_settings(struct kgd_dev *kgd,

void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev,

                        uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr)

{

	struct amdgpu_device *adev = get_amdgpu_device(kgd);



	lock_srbm(adev, 0, 0, 0, vmid);



	/*