Loading arch/arm/mach-zynq/common.c +0 −2 Original line number Diff line number Diff line Loading @@ -146,8 +146,6 @@ static void __init zynq_init_machine(void) platform_device_register(&zynq_cpuidle_device); platform_device_register_full(&devinfo); zynq_slcr_init(); } static void __init zynq_timer_init(void) Loading arch/arm/mach-zynq/slcr.c +7 −28 Original line number Diff line number Diff line Loading @@ -47,11 +47,6 @@ static struct regmap *zynq_slcr_regmap; */ static int zynq_slcr_write(u32 val, u32 offset) { if (!zynq_slcr_regmap) { writel(val, zynq_slcr_base + offset); return 0; } return regmap_write(zynq_slcr_regmap, offset, val); } Loading @@ -65,12 +60,7 @@ static int zynq_slcr_write(u32 val, u32 offset) */ static int zynq_slcr_read(u32 *val, u32 offset) { if (zynq_slcr_regmap) return regmap_read(zynq_slcr_regmap, offset, val); *val = readl(zynq_slcr_base + offset); return 0; } /** Loading Loading @@ -195,23 +185,6 @@ void zynq_slcr_cpu_state_write(int cpu, bool die) writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); } /** * zynq_slcr_init - Regular slcr driver init * Return: 0 on success, negative errno otherwise. * * Called early during boot from platform code to remap SLCR area. */ int __init zynq_slcr_init(void) { zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); if (IS_ERR(zynq_slcr_regmap)) { pr_err("%s: failed to find zynq-slcr\n", __func__); return -ENODEV; } return 0; } /** * zynq_early_slcr_init - Early slcr init function * Loading @@ -237,6 +210,12 @@ int __init zynq_early_slcr_init(void) np->data = (__force void *)zynq_slcr_base; zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); if (IS_ERR(zynq_slcr_regmap)) { pr_err("%s: failed to find zynq-slcr\n", __func__); return -ENODEV; } /* unlock the SLCR so that registers can be changed */ zynq_slcr_unlock(); Loading Loading
arch/arm/mach-zynq/common.c +0 −2 Original line number Diff line number Diff line Loading @@ -146,8 +146,6 @@ static void __init zynq_init_machine(void) platform_device_register(&zynq_cpuidle_device); platform_device_register_full(&devinfo); zynq_slcr_init(); } static void __init zynq_timer_init(void) Loading
arch/arm/mach-zynq/slcr.c +7 −28 Original line number Diff line number Diff line Loading @@ -47,11 +47,6 @@ static struct regmap *zynq_slcr_regmap; */ static int zynq_slcr_write(u32 val, u32 offset) { if (!zynq_slcr_regmap) { writel(val, zynq_slcr_base + offset); return 0; } return regmap_write(zynq_slcr_regmap, offset, val); } Loading @@ -65,12 +60,7 @@ static int zynq_slcr_write(u32 val, u32 offset) */ static int zynq_slcr_read(u32 *val, u32 offset) { if (zynq_slcr_regmap) return regmap_read(zynq_slcr_regmap, offset, val); *val = readl(zynq_slcr_base + offset); return 0; } /** Loading Loading @@ -195,23 +185,6 @@ void zynq_slcr_cpu_state_write(int cpu, bool die) writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); } /** * zynq_slcr_init - Regular slcr driver init * Return: 0 on success, negative errno otherwise. * * Called early during boot from platform code to remap SLCR area. */ int __init zynq_slcr_init(void) { zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); if (IS_ERR(zynq_slcr_regmap)) { pr_err("%s: failed to find zynq-slcr\n", __func__); return -ENODEV; } return 0; } /** * zynq_early_slcr_init - Early slcr init function * Loading @@ -237,6 +210,12 @@ int __init zynq_early_slcr_init(void) np->data = (__force void *)zynq_slcr_base; zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); if (IS_ERR(zynq_slcr_regmap)) { pr_err("%s: failed to find zynq-slcr\n", __func__); return -ENODEV; } /* unlock the SLCR so that registers can be changed */ zynq_slcr_unlock(); Loading