Commit 3317c26a authored by Like Xu's avatar Like Xu Committed by Peter Zijlstra
Browse files

perf/x86: Avoid touching LBR_TOS MSR for Arch LBR 



The Architecture LBR does not have MSR_LBR_TOS (0x000001c9).
In a guest that should support Architecture LBR, check_msr()
will be a non-related check for the architecture MSR 0x0
(IA32_P5_MC_ADDR) that is also not supported by KVM.

The failure will cause x86_pmu.lbr_nr = 0, thereby preventing
the initialization of the guest Arch LBR. Fix it by avoiding
this extraneous check in intel_pmu_init() for Arch LBR.

Fixes: 47125db2 ("perf/x86/intel/lbr: Support Architectural LBR")
Signed-off-by: default avatarLike Xu <like.xu@linux.intel.com>
[peterz: simpler still]
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20210430052247.3079672-1-like.xu@linux.intel.com
parent d07f6ca9

arch/x86/events/intel/core.c

+1 −1
Original line number Diff line number Diff line
@@ -6253,7 +6253,7 @@ __init int intel_pmu_init(void) 
	 * Check all LBT MSR here.

	 * Disable LBR access if any LBR MSRs can not be accessed.

	 */

	if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))

	if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))

		x86_pmu.lbr_nr = 0;

	for (i = 0; i < x86_pmu.lbr_nr; i++) {

		if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&