Commit 33151fb7 authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Set memclk levels to be at least 1 for dcn32 



[Why]
Cannot report 0 memclk levels even when SMU does not provide any.

[How]
When memclk levels reported by SMU is 0, set levels to 1.

Tested-by: default avatarMark Broadworth <mark.broadworth@amd.com>
Reviewed-by: default avatarMartin Leung <Martin.Leung@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarDillon Varone <Dillon.Varone@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4fd8575d

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+3 −0
Original line number Diff line number Diff line
@@ -669,6 +669,9 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) 
			&clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,

			&num_entries_per_clk->num_memclk_levels);



	/* memclk must have at least one level */

	num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1;



	dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,

			&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,

			&num_entries_per_clk->num_fclk_levels);