Commit 32dfbc03 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Matthias Brugger
Browse files

arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP table 



Add a device node for the CCI (cache coherent interconnect) and an OPP
table for it. The OPP table was taken from the downstream ChromeOS
kernel.

Signed-off-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230609072906.2784594-2-wenst@chromium.org


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent c26f779a

arch/arm64/boot/dts/mediatek/mt8186.dtsi

+101 −0
Original line number Diff line number Diff line
@@ -27,6 +27,99 @@ 
		rdma1 = &rdma1;

	};



	cci: cci {

		compatible = "mediatek,mt8186-cci";

		clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>,

			 <&apmixedsys CLK_APMIXED_MAINPLL>;

		clock-names = "cci", "intermediate";

		operating-points-v2 = <&cci_opp>;

	};



	cci_opp: opp-table-cci {

		compatible = "operating-points-v2";

		opp-shared;



		cci_opp_0: opp-500000000 {

			opp-hz = /bits/ 64 <500000000>;

			opp-microvolt = <600000>;

		};



		cci_opp_1: opp-560000000 {

			opp-hz = /bits/ 64 <560000000>;

			opp-microvolt = <675000>;

		};



		cci_opp_2: opp-612000000 {

			opp-hz = /bits/ 64 <612000000>;

			opp-microvolt = <693750>;

		};



		cci_opp_3: opp-682000000 {

			opp-hz = /bits/ 64 <682000000>;

			opp-microvolt = <718750>;

		};



		cci_opp_4: opp-752000000 {

			opp-hz = /bits/ 64 <752000000>;

			opp-microvolt = <743750>;

		};



		cci_opp_5: opp-822000000 {

			opp-hz = /bits/ 64 <822000000>;

			opp-microvolt = <768750>;

		};



		cci_opp_6: opp-875000000 {

			opp-hz = /bits/ 64 <875000000>;

			opp-microvolt = <781250>;

		};



		cci_opp_7: opp-927000000 {

			opp-hz = /bits/ 64 <927000000>;

			opp-microvolt = <800000>;

		};



		cci_opp_8: opp-980000000 {

			opp-hz = /bits/ 64 <980000000>;

			opp-microvolt = <818750>;

		};



		cci_opp_9: opp-1050000000 {

			opp-hz = /bits/ 64 <1050000000>;

			opp-microvolt = <843750>;

		};



		cci_opp_10: opp-1120000000 {

			opp-hz = /bits/ 64 <1120000000>;

			opp-microvolt = <862500>;

		};



		cci_opp_11: opp-1155000000 {

			opp-hz = /bits/ 64 <1155000000>;

			opp-microvolt = <887500>;

		};



		cci_opp_12: opp-1190000000 {

			opp-hz = /bits/ 64 <1190000000>;

			opp-microvolt = <906250>;

		};



		cci_opp_13: opp-1260000000 {

			opp-hz = /bits/ 64 <1260000000>;

			opp-microvolt = <950000>;

		};



		cci_opp_14: opp-1330000000 {

			opp-hz = /bits/ 64 <1330000000>;

			opp-microvolt = <993750>;

		};



		cci_opp_15: opp-1400000000 {

			opp-hz = /bits/ 64 <1400000000>;

			opp-microvolt = <1031250>;

		};

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -83,6 +176,7 @@ 
			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

			mediatek,cci = <&cci>;

		};



		cpu1: cpu@100 {
@@ -101,6 +195,7 @@ 
			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

			mediatek,cci = <&cci>;

		};



		cpu2: cpu@200 {
@@ -119,6 +214,7 @@ 
			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

			mediatek,cci = <&cci>;

		};



		cpu3: cpu@300 {
@@ -137,6 +233,7 @@ 
			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

			mediatek,cci = <&cci>;

		};



		cpu4: cpu@400 {
@@ -155,6 +252,7 @@ 
			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

			mediatek,cci = <&cci>;

		};



		cpu5: cpu@500 {
@@ -173,6 +271,7 @@ 
			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			#cooling-cells = <2>;

			mediatek,cci = <&cci>;

		};



		cpu6: cpu@600 {
@@ -191,6 +290,7 @@ 
			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			#cooling-cells = <2>;

			mediatek,cci = <&cci>;

		};



		cpu7: cpu@700 {
@@ -209,6 +309,7 @@ 
			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			#cooling-cells = <2>;

			mediatek,cci = <&cci>;

		};



		idle-states {