Commit 32d2ca0e authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/32: Refactor booke critical registers saving 



Refactor booke critical registers saving into a few macros
and move it into the exception prolog directly.

Keep the dedicated transfert_to_handler entry point for the
moment allthough they are empty. They will be removed in a
later patch to reduce churn.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/269171496f1f5f22afa621695bded22976c9d48d.1615552867.git.christophe.leroy@csgroup.eu
parent 8f844c06

arch/powerpc/kernel/entry_32.S

+0 −33
Original line number Diff line number Diff line
@@ -51,49 +51,16 @@ 
#ifdef CONFIG_BOOKE

	.globl	mcheck_transfer_to_handler

mcheck_transfer_to_handler:

	mfspr	r0,SPRN_DSRR0

	stw	r0,_DSRR0(r11)

	mfspr	r0,SPRN_DSRR1

	stw	r0,_DSRR1(r11)

	/* fall through */

_ASM_NOKPROBE_SYMBOL(mcheck_transfer_to_handler)



	.globl	debug_transfer_to_handler

debug_transfer_to_handler:

	mfspr	r0,SPRN_CSRR0

	stw	r0,_CSRR0(r11)

	mfspr	r0,SPRN_CSRR1

	stw	r0,_CSRR1(r11)

	/* fall through */

_ASM_NOKPROBE_SYMBOL(debug_transfer_to_handler)



	.globl	crit_transfer_to_handler

crit_transfer_to_handler:

#ifdef CONFIG_PPC_BOOK3E_MMU

	mfspr	r0,SPRN_MAS0

	stw	r0,MAS0(r11)

	mfspr	r0,SPRN_MAS1

	stw	r0,MAS1(r11)

	mfspr	r0,SPRN_MAS2

	stw	r0,MAS2(r11)

	mfspr	r0,SPRN_MAS3

	stw	r0,MAS3(r11)

	mfspr	r0,SPRN_MAS6

	stw	r0,MAS6(r11)

#ifdef CONFIG_PHYS_64BIT

	mfspr	r0,SPRN_MAS7

	stw	r0,MAS7(r11)

#endif /* CONFIG_PHYS_64BIT */

#endif /* CONFIG_PPC_BOOK3E_MMU */

#ifdef CONFIG_44x

	mfspr	r0,SPRN_MMUCR

	stw	r0,MMUCR(r11)

#endif

	mfspr	r0,SPRN_SRR0

	stw	r0,_SRR0(r11)

	mfspr	r0,SPRN_SRR1

	stw	r0,_SRR1(r11)



	/* fall through */

_ASM_NOKPROBE_SYMBOL(crit_transfer_to_handler)

#endif

arch/powerpc/kernel/head_booke.h

+41 −0
Original line number Diff line number Diff line
@@ -229,6 +229,36 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) 
	SAVE_4GPRS(3, r11);						     \

	SAVE_2GPRS(7, r11)



#define SAVE_xSRR(xSRR)			\

	mfspr	r0,SPRN_##xSRR##0;	\

	stw	r0,_##xSRR##0(r1);	\

	mfspr	r0,SPRN_##xSRR##1;	\

	stw	r0,_##xSRR##1(r1)





.macro SAVE_MMU_REGS

#ifdef CONFIG_PPC_BOOK3E_MMU

	mfspr	r0,SPRN_MAS0

	stw	r0,MAS0(r1)

	mfspr	r0,SPRN_MAS1

	stw	r0,MAS1(r1)

	mfspr	r0,SPRN_MAS2

	stw	r0,MAS2(r1)

	mfspr	r0,SPRN_MAS3

	stw	r0,MAS3(r1)

	mfspr	r0,SPRN_MAS6

	stw	r0,MAS6(r1)

#ifdef CONFIG_PHYS_64BIT

	mfspr	r0,SPRN_MAS7

	stw	r0,MAS7(r1)

#endif /* CONFIG_PHYS_64BIT */

#endif /* CONFIG_PPC_BOOK3E_MMU */

#ifdef CONFIG_44x

	mfspr	r0,SPRN_MMUCR

	stw	r0,MMUCR(r1)

#endif

.endm



#define CRITICAL_EXCEPTION_PROLOG(intno) \

		EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1)

#define DEBUG_EXCEPTION_PROLOG \
@@ -271,6 +301,8 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) 
	START_EXCEPTION(label);						\

	CRITICAL_EXCEPTION_PROLOG(intno);				\

	addi	r3,r1,STACK_FRAME_OVERHEAD;				\

	SAVE_MMU_REGS;							\

	SAVE_xSRR(SRR);							\

	EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \

			  crit_transfer_to_handler, ret_from_crit_exc)
@@ -280,6 +312,10 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) 
	mfspr	r5,SPRN_ESR;					\

	stw	r5,_ESR(r11);					\

	addi	r3,r1,STACK_FRAME_OVERHEAD;			\

	SAVE_xSRR(DSRR);					\

	SAVE_xSRR(CSRR);					\

	SAVE_MMU_REGS;						\

	SAVE_xSRR(SRR);						\

	EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \

			  mcheck_transfer_to_handler, ret_from_mcheck_exc)
@@ -363,6 +399,9 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) 
2:	mfspr	r4,SPRN_DBSR;						      \

	stw	r4,_ESR(r11);		/* DebugException takes DBSR in _ESR */\

	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \

	SAVE_xSRR(CSRR);						      \

	SAVE_MMU_REGS;							      \

	SAVE_xSRR(SRR);							      \

	EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), debug_transfer_to_handler, ret_from_debug_exc)



#define DEBUG_CRIT_EXCEPTION						      \
@@ -417,6 +456,8 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) 
2:	mfspr	r4,SPRN_DBSR;						      \

	stw	r4,_ESR(r11);		/* DebugException takes DBSR in _ESR */\

	addi	r3,r1,STACK_FRAME_OVERHEAD;				      \

	SAVE_MMU_REGS;							      \

	SAVE_xSRR(SRR);							      \

	EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), crit_transfer_to_handler, ret_from_crit_exc)



#define DATA_STORAGE_EXCEPTION						      \