Commit 32c3d9b0 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2021-01-27' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



- HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (Anshuman)
- Fix DP vswing settings and handling (Imre, Ville)
- Various display code clean-up (Jani, Ville)
- Various display refactoring, including split out of pps, aux, and fdi (Ja\
ni, Dave)
- Add DG1 missing workarounds (Jose)
- Fix display color conversion (Chris, Ville)
- Try to guess PCH type even without ISA bridge (Zhenyu)
- More backlight refactor (Lyude)
- Support two CSC module on gen11 and later (Lee)
- Async flips for all ilk+ platforms (Ville)
- Clear color support for TGL (RK)
- Add a helper to read data from a GEM object page (Imre)
- VRR/Adaptive Sync Enabling on DP/eDP for TGL+ (Manasi, Ville Aditya)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210127140822.GA711686@intel.com
parents bc96ad67 784953a4

drivers/gpu/drm/drm_dp_helper.c

+1 −82
Original line number Diff line number Diff line
@@ -1236,7 +1236,7 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 
	return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&

		dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&

		dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&

		!drm_dp_has_quirk(desc, 0, DP_DPCD_QUIRK_NO_SINK_COUNT);

		!drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT);

}

EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
@@ -1957,87 +1957,6 @@ drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch) 
#undef DEVICE_ID_ANY

#undef DEVICE_ID



struct edid_quirk {

	u8 mfg_id[2];

	u8 prod_id[2];

	u32 quirks;

};



#define MFG(first, second) { (first), (second) }

#define PROD_ID(first, second) { (first), (second) }



/*

 * Some devices have unreliable OUIDs where they don't set the device ID

 * correctly, and as a result we need to use the EDID for finding additional

 * DP quirks in such cases.

 */

static const struct edid_quirk edid_quirk_list[] = {

	/* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation

	 * only supports DPCD backlight controls

	 */

	{ MFG(0x4c, 0x83), PROD_ID(0x41, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },

	/*

	 * Some Dell CML 2020 systems have panels support both AUX and PWM

	 * backlight control, and some only support AUX backlight control. All

	 * said panels start up in AUX mode by default, and we don't have any

	 * support for disabling HDR mode on these panels which would be

	 * required to switch to PWM backlight control mode (plus, I'm not

	 * even sure we want PWM backlight controls over DPCD backlight

	 * controls anyway...). Until we have a better way of detecting these,

	 * force DPCD backlight mode on all of them.

	 */

	{ MFG(0x06, 0xaf), PROD_ID(0x9b, 0x32), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },

	{ MFG(0x06, 0xaf), PROD_ID(0xeb, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },

	{ MFG(0x4d, 0x10), PROD_ID(0xc7, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },

	{ MFG(0x4d, 0x10), PROD_ID(0xe6, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },

	{ MFG(0x4c, 0x83), PROD_ID(0x47, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },

	{ MFG(0x09, 0xe5), PROD_ID(0xde, 0x08), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },

};



#undef MFG

#undef PROD_ID



/**

 * drm_dp_get_edid_quirks() - Check the EDID of a DP device to find additional

 * DP-specific quirks

 * @edid: The EDID to check

 *

 * While OUIDs are meant to be used to recognize a DisplayPort device, a lot

 * of manufacturers don't seem to like following standards and neglect to fill

 * the dev-ID in, making it impossible to only use OUIDs for determining

 * quirks in some cases. This function can be used to check the EDID and look

 * up any additional DP quirks. The bits returned by this function correspond

 * to the quirk bits in &drm_dp_quirk.

 *

 * Returns: a bitmask of quirks, if any. The driver can check this using

 * drm_dp_has_quirk().

 */

u32 drm_dp_get_edid_quirks(const struct edid *edid)

{

	const struct edid_quirk *quirk;

	u32 quirks = 0;

	int i;



	if (!edid)

		return 0;



	for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {

		quirk = &edid_quirk_list[i];

		if (memcmp(quirk->mfg_id, edid->mfg_id,

			   sizeof(edid->mfg_id)) == 0 &&

		    memcmp(quirk->prod_id, edid->prod_code,

			   sizeof(edid->prod_code)) == 0)

			quirks |= quirk->quirks;

	}



	DRM_DEBUG_KMS("DP sink: EDID mfg %*phD prod-ID %*phD quirks: 0x%04x\n",

		      (int)sizeof(edid->mfg_id), edid->mfg_id,

		      (int)sizeof(edid->prod_code), edid->prod_code, quirks);



	return quirks;

}

EXPORT_SYMBOL(drm_dp_get_edid_quirks);



/**

 * drm_dp_read_desc - read sink/branch descriptor from DPCD

 * @aux: DisplayPort AUX channel

drivers/gpu/drm/drm_dp_mst_topology.c

+1 −2
Original line number Diff line number Diff line
@@ -5824,8 +5824,7 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port) 
	if (drm_dp_read_desc(port->mgr->aux, &desc, true))

		return NULL;



	if (drm_dp_has_quirk(&desc, 0,

			     DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) &&

	if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) &&

	    port->mgr->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 &&

	    port->parent == port->mgr->mst_primary) {

		u8 downstreamport;

drivers/gpu/drm/i915/Makefile

+6 −0
Original line number Diff line number Diff line
@@ -201,14 +201,17 @@ i915-y += \ 
	display/intel_color.o \

	display/intel_combo_phy.o \

	display/intel_connector.o \

	display/intel_crtc.o \

	display/intel_csr.o \

	display/intel_cursor.o \

	display/intel_display.o \

	display/intel_display_power.o \

	display/intel_dpio_phy.o \

	display/intel_dpll.o \

	display/intel_dpll_mgr.o \

	display/intel_dsb.o \

	display/intel_fbc.o \

	display/intel_fdi.o \

	display/intel_fifo_underrun.o \

	display/intel_frontbuffer.o \

	display/intel_global_state.o \
@@ -240,6 +243,7 @@ i915-y += \ 
	display/intel_crt.o \

	display/intel_ddi.o \

	display/intel_dp.o \

	display/intel_dp_aux.o \

	display/intel_dp_aux_backlight.o \

	display/intel_dp_hdcp.o \

	display/intel_dp_link_training.o \
@@ -253,9 +257,11 @@ i915-y += \ 
	display/intel_lspcon.o \

	display/intel_lvds.o \

	display/intel_panel.o \

	display/intel_pps.o \

	display/intel_sdvo.o \

	display/intel_tv.o \

	display/intel_vdsc.o \

	display/intel_vrr.o \

	display/vlv_dsi.o \

	display/vlv_dsi_pll.o

drivers/gpu/drm/i915/display/intel_atomic_plane.c

+1 −1
Original line number Diff line number Diff line
@@ -452,7 +452,7 @@ void intel_update_plane(struct intel_plane *plane, 
	trace_intel_update_plane(&plane->base, crtc);



	if (crtc_state->uapi.async_flip && plane->async_flip)

		plane->async_flip(plane, crtc_state, plane_state);

		plane->async_flip(plane, crtc_state, plane_state, true);

	else

		plane->update_plane(plane, crtc_state, plane_state);

}

drivers/gpu/drm/i915/display/intel_color.c

+16 −0
Original line number Diff line number Diff line
@@ -1485,6 +1485,7 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state) 


static int ivb_color_check(struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

	bool limited_color_range = ilk_csc_limited_range(crtc_state);

	int ret;
@@ -1492,6 +1493,13 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state) 
	if (ret)

		return ret;



	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&

	    crtc_state->hw.ctm) {

		drm_dbg_kms(&dev_priv->drm,

			    "YCBCR and CTM together are not possible\n");

		return -EINVAL;

	}



	crtc_state->gamma_enable =

		(crtc_state->hw.gamma_lut ||

		 crtc_state->hw.degamma_lut) &&
@@ -1525,12 +1533,20 @@ static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state) 


static int glk_color_check(struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

	int ret;



	ret = check_luts(crtc_state);

	if (ret)

		return ret;



	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&

	    crtc_state->hw.ctm) {

		drm_dbg_kms(&dev_priv->drm,

			    "YCBCR and CTM together are not possible\n");

		return -EINVAL;

	}



	crtc_state->gamma_enable =

		crtc_state->hw.gamma_lut &&

		!crtc_state->c8_planes;