Commit 3295cf12 authored by Jack Zhu's avatar Jack Zhu Committed by Mauro Carvalho Chehab
Browse files

media: cadence: Add support for external dphy 



Add support for external MIPI D-PHY.

Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarJack Zhu <jack.zhu@starfivetech.com>
Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@kernel.org>
parent e0b9ce38

drivers/media/platform/cadence/cdns-csi2rx.c

+56 −10
Original line number Diff line number Diff line
@@ -31,6 +31,12 @@ 
#define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane)	((plane) << (16 + (llane) * 4))

#define CSI2RX_STATIC_CFG_LANES_MASK			GENMASK(11, 8)



#define CSI2RX_DPHY_LANE_CTRL_REG		0x40

#define CSI2RX_DPHY_CL_RST			BIT(16)

#define CSI2RX_DPHY_DL_RST(i)			BIT((i) + 12)

#define CSI2RX_DPHY_CL_EN			BIT(4)

#define CSI2RX_DPHY_DL_EN(i)			BIT(i)



#define CSI2RX_STREAM_BASE(n)		(((n) + 1) * 0x100)



#define CSI2RX_STREAM_CTRL_REG(n)		(CSI2RX_STREAM_BASE(n) + 0x000)
@@ -105,6 +111,24 @@ static void csi2rx_reset(struct csi2rx_priv *csi2rx) 
	writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG);

}



static int csi2rx_configure_ext_dphy(struct csi2rx_priv *csi2rx)

{

	union phy_configure_opts opts = { };

	int ret;



	ret = phy_power_on(csi2rx->dphy);

	if (ret)

		return ret;



	ret = phy_configure(csi2rx->dphy, &opts);

	if (ret) {

		phy_power_off(csi2rx->dphy);

		return ret;

	}



	return 0;

}



static int csi2rx_start(struct csi2rx_priv *csi2rx)

{

	unsigned int i;
@@ -144,6 +168,17 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) 
	if (ret)

		goto err_disable_pclk;



	/* Enable DPHY clk and data lanes. */

	if (csi2rx->dphy) {

		reg = CSI2RX_DPHY_CL_EN | CSI2RX_DPHY_CL_RST;

		for (i = 0; i < csi2rx->num_lanes; i++) {

			reg |= CSI2RX_DPHY_DL_EN(csi2rx->lanes[i] - 1);

			reg |= CSI2RX_DPHY_DL_RST(csi2rx->lanes[i] - 1);

		}



		writel(reg, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG);

	}



	/*

	 * Create a static mapping between the CSI virtual channels

	 * and the output stream.
@@ -177,10 +212,22 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) 
		goto err_disable_pixclk;



	reset_control_deassert(csi2rx->sys_rst);



	if (csi2rx->dphy) {

		ret = csi2rx_configure_ext_dphy(csi2rx);

		if (ret) {

			dev_err(csi2rx->dev,

				"Failed to configure external DPHY: %d\n", ret);

			goto err_disable_sysclk;

		}

	}



	clk_disable_unprepare(csi2rx->p_clk);



	return 0;



err_disable_sysclk:

	clk_disable_unprepare(csi2rx->sys_clk);

err_disable_pixclk:

	for (; i > 0; i--) {

		reset_control_assert(csi2rx->pixel_rst[i - 1]);
@@ -213,6 +260,13 @@ static void csi2rx_stop(struct csi2rx_priv *csi2rx) 


	if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false))

		dev_warn(csi2rx->dev, "Couldn't disable our subdev\n");



	if (csi2rx->dphy) {

		writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG);



		if (phy_power_off(csi2rx->dphy))

			dev_warn(csi2rx->dev, "Couldn't power off DPHY\n");

	}

}



static int csi2rx_s_stream(struct v4l2_subdev *subdev, int enable)
@@ -328,15 +382,6 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, 
		return PTR_ERR(csi2rx->dphy);

	}



	/*

	 * FIXME: Once we'll have external D-PHY support, the check

	 * will need to be removed.

	 */

	if (csi2rx->dphy) {

		dev_err(&pdev->dev, "External D-PHY not supported yet\n");

		return -EINVAL;

	}



	ret = clk_prepare_enable(csi2rx->p_clk);

	if (ret) {

		dev_err(&pdev->dev, "Couldn't prepare and enable P clock\n");
@@ -366,7 +411,7 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, 
	 * FIXME: Once we'll have internal D-PHY support, the check

	 * will need to be removed.

	 */

	if (csi2rx->has_internal_dphy) {

	if (!csi2rx->dphy && csi2rx->has_internal_dphy) {

		dev_err(&pdev->dev, "Internal D-PHY not supported yet\n");

		return -EINVAL;

	}
@@ -492,6 +537,7 @@ static int csi2rx_probe(struct platform_device *pdev) 
	dev_info(&pdev->dev,

		 "Probed CSI2RX with %u/%u lanes, %u streams, %s D-PHY\n",

		 csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams,

		 csi2rx->dphy ? "external" :

		 csi2rx->has_internal_dphy ? "internal" : "no");



	return 0;