Commit 3270ffe8 authored by Will McVicker's avatar Will McVicker Committed by Sylwester Nawrocki
Browse files

clk: samsung: add support for CPU clocks 



Adds 'struct samsung_cpu_clock' and corresponding CPU clock registration
function to the samsung common clk driver. This allows samsung clock
drivers to register their CPU clocks with the samsung_cmu_register_one()
API.

Currently the exynos5433 apollo and atlas clks have their own custom
init functions to handle registering their CPU clocks. With this patch
we can drop their custom CLK_OF_DECLARE functions and directly call
samsung_cmu_register_one().

Signed-off-by: default avatarWill McVicker <willmcvicker@google.com>
Tested-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211014195347.3635601-2-willmcvicker@google.com


Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 7dd05578

drivers/clk/samsung/clk-cpu.c

+18 −0
Original line number Diff line number Diff line
@@ -469,3 +469,21 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, 
	kfree(cpuclk);

	return ret;

}



void __init samsung_clk_register_cpu(struct samsung_clk_provider *ctx,

		const struct samsung_cpu_clock *list, unsigned int nr_clk)

{

	unsigned int idx;

	unsigned int num_cfgs;

	struct clk_hw **hws = ctx->clk_data.hws;



	for (idx = 0; idx < nr_clk; idx++, list++) {

		/* find count of configuration rates in cfg */

		for (num_cfgs = 0; list->cfg[num_cfgs].prate != 0; )

			num_cfgs++;



		exynos_register_cpu_clock(ctx, list->id, list->name, hws[list->parent_id],

				hws[list->alt_parent_id], list->offset, list->cfg, num_cfgs,

				list->flags);

	}

}

drivers/clk/samsung/clk.c

+2 −0
Original line number Diff line number Diff line
@@ -378,6 +378,8 @@ struct samsung_clk_provider * __init samsung_cmu_register_one( 
		samsung_clk_extended_sleep_init(reg_base,

			cmu->clk_regs, cmu->nr_clk_regs,

			cmu->suspend_regs, cmu->nr_suspend_regs);

	if (cmu->cpu_clks)

		samsung_clk_register_cpu(ctx, cmu->cpu_clks, cmu->nr_cpu_clks);



	samsung_clk_of_add_provider(np, ctx);

drivers/clk/samsung/clk.h

+26 −0
Original line number Diff line number Diff line
@@ -271,6 +271,27 @@ struct samsung_pll_clock { 
	__PLL(_typ, _id, _name, _pname, CLK_GET_RATE_NOCACHE, _lock,	\

	      _con, _rtable)



struct samsung_cpu_clock {

	unsigned int	id;

	const char	*name;

	unsigned int	parent_id;

	unsigned int	alt_parent_id;

	unsigned long	flags;

	int		offset;

	const struct exynos_cpuclk_cfg_data *cfg;

};



#define CPU_CLK(_id, _name, _pid, _apid, _flags, _offset, _cfg) \

	{							\

		.id		  = _id,			\

		.name		  = _name,			\

		.parent_id	  = _pid,			\

		.alt_parent_id	  = _apid,			\

		.flags		  = _flags,			\

		.offset		  = _offset,			\

		.cfg		  = _cfg,			\

	}



struct samsung_clock_reg_cache {

	struct list_head node;

	void __iomem *reg_base;
@@ -301,6 +322,9 @@ struct samsung_cmu_info { 
	unsigned int nr_fixed_factor_clks;

	/* total number of clocks with IDs assigned*/

	unsigned int nr_clk_ids;

	/* list of cpu clocks and respective count */

	const struct samsung_cpu_clock *cpu_clks;

	unsigned int nr_cpu_clks;



	/* list and number of clocks registers */

	const unsigned long *clk_regs;
@@ -350,6 +374,8 @@ extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, 
extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,

			const struct samsung_pll_clock *pll_list,

			unsigned int nr_clk, void __iomem *base);

extern void samsung_clk_register_cpu(struct samsung_clk_provider *ctx,

		const struct samsung_cpu_clock *list, unsigned int nr_clk);



extern struct samsung_clk_provider __init *samsung_cmu_register_one(

			struct device_node *,