Unverified Commit 325c81e3 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'at91-fixes-5.15-2' of... 

Merge tag 'at91-fixes-5.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/fixes

AT91 fixes #2 for 5.15:

- More fixes for AT91 platform power management code related to the
  introduction of sama7g5:
  - management of DDR3L regulator rails for sama7g5ek
  - loading of TLB on different cores

- PIO controller slew-rate settings for sama7g5ek: be aligned with
  datasheet requirements.

* tag 'at91-fixes-5.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: dts: at91: sama7g5ek: to not touch slew-rate for SDMMC pins
  ARM: dts: at91: sama7g5ek: use proper slew-rate settings for GMACs
  ARM: at91: pm: preload base address of controllers in tlb
  ARM: at91: pm: group constants and addresses loading
  ARM: dts: at91: sama7g5ek: add suspend voltage for ddr3l rail

Link: https://lore.kernel.org/r/20211004114344.19304-1-nicolas.ferre@microchip.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents dd6a2ed8 dbe68bc9

arch/arm/boot/dts/at91-sama7g5ek.dts

+30 −6
Original line number Diff line number Diff line
@@ -196,11 +196,13 @@ 


					regulator-state-standby {

						regulator-on-in-suspend;

						regulator-suspend-microvolt = <1350000>;

						regulator-mode = <4>;

					};



					regulator-state-mem {

						regulator-on-in-suspend;

						regulator-suspend-microvolt = <1350000>;

						regulator-mode = <4>;

					};

				};
@@ -353,7 +355,10 @@ 
	#address-cells = <1>;

	#size-cells = <0>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>;

	pinctrl-0 = <&pinctrl_gmac0_default

		     &pinctrl_gmac0_mdio_default

		     &pinctrl_gmac0_txck_default

		     &pinctrl_gmac0_phy_irq>;

	phy-mode = "rgmii-id";

	status = "okay";
@@ -368,7 +373,9 @@ 
	#address-cells = <1>;

	#size-cells = <0>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>;

	pinctrl-0 = <&pinctrl_gmac1_default

		     &pinctrl_gmac1_mdio_default

		     &pinctrl_gmac1_phy_irq>;

	phy-mode = "rmii";

	status = "okay";
@@ -423,14 +430,20 @@ 
			 <PIN_PA15__G0_TXEN>,

			 <PIN_PA30__G0_RXCK>,

			 <PIN_PA18__G0_RXDV>,

			 <PIN_PA22__G0_MDC>,

			 <PIN_PA23__G0_MDIO>,

			 <PIN_PA25__G0_125CK>;

		slew-rate = <0>;

		bias-disable;

	};



	pinctrl_gmac0_mdio_default: gmac0_mdio_default {

		pinmux = <PIN_PA22__G0_MDC>,

			 <PIN_PA23__G0_MDIO>;

		bias-disable;

	};



	pinctrl_gmac0_txck_default: gmac0_txck_default {

		pinmux = <PIN_PA24__G0_TXCK>;

		slew-rate = <0>;

		bias-pull-up;

	};
@@ -447,8 +460,13 @@ 
			 <PIN_PD25__G1_RX0>,

			 <PIN_PD26__G1_RX1>,

			 <PIN_PD27__G1_RXER>,

			 <PIN_PD24__G1_RXDV>,

			 <PIN_PD28__G1_MDC>,

			 <PIN_PD24__G1_RXDV>;

		slew-rate = <0>;

		bias-disable;

	};



	pinctrl_gmac1_mdio_default: gmac1_mdio_default {

		pinmux = <PIN_PD28__G1_MDC>,

			 <PIN_PD29__G1_MDIO>;

		bias-disable;

	};
@@ -540,6 +558,7 @@ 
				 <PIN_PA8__SDMMC0_DAT5>,

				 <PIN_PA9__SDMMC0_DAT6>,

				 <PIN_PA10__SDMMC0_DAT7>;

			slew-rate = <0>;

			bias-pull-up;

		};
@@ -547,6 +566,7 @@ 
			pinmux = <PIN_PA0__SDMMC0_CK>,

				 <PIN_PA2__SDMMC0_RSTN>,

				 <PIN_PA11__SDMMC0_DS>;

			slew-rate = <0>;

			bias-pull-up;

		};

	};
@@ -558,6 +578,7 @@ 
				 <PIN_PC0__SDMMC1_DAT1>,

				 <PIN_PC1__SDMMC1_DAT2>,

				 <PIN_PC2__SDMMC1_DAT3>;

			slew-rate = <0>;

			bias-pull-up;

		};
@@ -566,6 +587,7 @@ 
				 <PIN_PB28__SDMMC1_RSTN>,

				 <PIN_PC5__SDMMC1_1V8SEL>,

				 <PIN_PC4__SDMMC1_CD>;

			slew-rate = <0>;

			bias-pull-up;

		};

	};
@@ -577,11 +599,13 @@ 
				 <PIN_PD6__SDMMC2_DAT1>,

				 <PIN_PD7__SDMMC2_DAT2>,

				 <PIN_PD8__SDMMC2_DAT3>;

			slew-rate = <0>;

			bias-pull-up;

		};



		ck {

			pinmux = <PIN_PD4__SDMMC2_CK>;

			slew-rate = <0>;

			bias-pull-up;

		};

	};

arch/arm/mach-at91/pm_suspend.S

+33 −9
Original line number Diff line number Diff line
@@ -1014,31 +1014,55 @@ ENTRY(at91_pm_suspend_in_sram) 
	mov	tmp1, #0

	mcr	p15, 0, tmp1, c7, c10, 4



	/* Flush tlb. */

	mov	r4, #0

	mcr	p15, 0, r4, c8, c7, 0



	ldr	tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]

	str	tmp1, .mckr_offset

	ldr	tmp1, [r0, #PM_DATA_PMC_VERSION]

	str	tmp1, .pmc_version

	ldr	tmp1, [r0, #PM_DATA_MEMCTRL]

	str	tmp1, .memtype

	ldr	tmp1, [r0, #PM_DATA_MODE]

	str	tmp1, .pm_mode



	/*

	 * ldrne below are here to preload their address in the TLB as access

	 * to RAM may be limited while in self-refresh.

	 */

	ldr	tmp1, [r0, #PM_DATA_PMC]

	str	tmp1, .pmc_base

	cmp	tmp1, #0

	ldrne	tmp2, [tmp1, #0]



	ldr	tmp1, [r0, #PM_DATA_RAMC0]

	str	tmp1, .sramc_base

	cmp	tmp1, #0

	ldrne	tmp2, [tmp1, #0]



	ldr	tmp1, [r0, #PM_DATA_RAMC1]

	str	tmp1, .sramc1_base

	cmp	tmp1, #0

	ldrne	tmp2, [tmp1, #0]



#ifndef CONFIG_SOC_SAM_V4_V5

	/* ldrne below are here to preload their address in the TLB */

	ldr	tmp1, [r0, #PM_DATA_RAMC_PHY]

	str	tmp1, .sramc_phy_base

	ldr	tmp1, [r0, #PM_DATA_MEMCTRL]

	str	tmp1, .memtype

	ldr	tmp1, [r0, #PM_DATA_MODE]

	str	tmp1, .pm_mode

	ldr	tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]

	str	tmp1, .mckr_offset

	ldr	tmp1, [r0, #PM_DATA_PMC_VERSION]

	str	tmp1, .pmc_version

	/* Both ldrne below are here to preload their address in the TLB */

	cmp	tmp1, #0

	ldrne	tmp2, [tmp1, #0]



	ldr	tmp1, [r0, #PM_DATA_SHDWC]

	str	tmp1, .shdwc

	cmp	tmp1, #0

	ldrne	tmp2, [tmp1, #0]



	ldr	tmp1, [r0, #PM_DATA_SFRBU]

	str	tmp1, .sfrbu

	cmp	tmp1, #0

	ldrne	tmp2, [tmp1, #0x10]

#endif



	/* Active the self-refresh mode */

	at91_sramc_self_refresh_ena