Commit 3254e0b9 authored by Alexandru Tachici's avatar Alexandru Tachici Committed by David S. Miller
Browse files

ethtool: Add 10base-T1L link mode entry 



Add entry for the 10base-T1L full duplex mode.

Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Reviewed-by: default avatarOleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: default avatarAlexandru Tachici <alexandru.tachici@analog.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 411a1476

drivers/net/phy/phy-core.c

+2 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
 */

const char *phy_speed_to_str(int speed)

{

	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,

	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 93,

		"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "

		"If a speed or mode has been added please update phy_speed_to_str "

		"and the PHY settings array.\n");
@@ -176,6 +176,7 @@ static const struct phy_setting settings[] = { 
	/* 10M */

	PHY_SETTING(     10, FULL,     10baseT_Full		),

	PHY_SETTING(     10, HALF,     10baseT_Half		),

	PHY_SETTING(     10, FULL,     10baseT1L_Full		),

};

#undef PHY_SETTING

drivers/net/phy/phy_device.c

+2 −1
Original line number Diff line number Diff line
@@ -90,8 +90,9 @@ const int phy_10_100_features_array[4] = { 
};

EXPORT_SYMBOL_GPL(phy_10_100_features_array);



const int phy_basic_t1_features_array[2] = {

const int phy_basic_t1_features_array[3] = {

	ETHTOOL_LINK_MODE_TP_BIT,

	ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,

	ETHTOOL_LINK_MODE_100baseT1_Full_BIT,

};

EXPORT_SYMBOL_GPL(phy_basic_t1_features_array);

drivers/net/phy/phylink.c

+3 −1
Original line number Diff line number Diff line
@@ -168,8 +168,10 @@ static void phylink_caps_to_linkmodes(unsigned long *linkmodes, 
	if (caps & MAC_10HD)

		__set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, linkmodes);



	if (caps & MAC_10FD)

	if (caps & MAC_10FD) {

		__set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, linkmodes);

		__set_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, linkmodes);

	}



	if (caps & MAC_100HD) {

		__set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, linkmodes);

include/linux/phy.h

+1 −1
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ extern const int phy_basic_ports_array[3]; 
extern const int phy_fibre_port_array[1];

extern const int phy_all_ports_features_array[7];

extern const int phy_10_100_features_array[4];

extern const int phy_basic_t1_features_array[2];

extern const int phy_basic_t1_features_array[3];

extern const int phy_gbit_features_array[2];

extern const int phy_10gbit_features_array[1];

include/uapi/linux/ethtool.h

+1 −0
Original line number Diff line number Diff line
@@ -1691,6 +1691,7 @@ enum ethtool_link_mode_bit_indices { 
	ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT	 = 89,

	ETHTOOL_LINK_MODE_100baseFX_Half_BIT		 = 90,

	ETHTOOL_LINK_MODE_100baseFX_Full_BIT		 = 91,

	ETHTOOL_LINK_MODE_10baseT1L_Full_BIT		 = 92,

	/* must be last entry */

	__ETHTOOL_LINK_MODE_MASK_NBITS

};