Commit 32431fb2 authored by Vineeth Pillai's avatar Vineeth Pillai Committed by Paolo Bonzini
Browse files

hyperv: SVM enlightened TLB flush support flag 



Bit 22 of HYPERV_CPUID_FEATURES.EDX is specific to SVM and specifies
support for enlightened TLB flush. With this enlightenment enabled,
ASID invalidations flushes only gva->hpa entries. To flush TLB entries
derived from NPT, hypercalls should be used
(HvFlushGuestPhysicalAddressSpace or HvFlushGuestPhysicalAddressList)

Signed-off-by: default avatarVineeth Pillai <viremana@linux.microsoft.com>
Reviewed-by: default avatarMichael Kelley <mikelley@microsoft.com>
Message-Id: <a060f872d0df1955e52e30b877b3300485edb27c.1622730232.git.viremana@linux.microsoft.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent a6c776a9

arch/x86/include/asm/hyperv-tlfs.h

+9 −0
Original line number Diff line number Diff line
@@ -138,6 +138,15 @@ 
#define HV_X64_NESTED_GUEST_MAPPING_FLUSH		BIT(18)

#define HV_X64_NESTED_MSR_BITMAP			BIT(19)



/*

 * This is specific to AMD and specifies that enlightened TLB flush is

 * supported. If guest opts in to this feature, ASID invalidations only

 * flushes gva -> hpa mapping entries. To flush the TLB entries derived

 * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace

 * or HvFlushGuestPhysicalAddressList).

 */

#define HV_X64_NESTED_ENLIGHTENED_TLB			BIT(22)



/* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */

#define HV_PARAVISOR_PRESENT				BIT(0)