Commit 323b91ac authored by Muhammad Sammar's avatar Muhammad Sammar Committed by Saeed Mahameed
Browse files

net/mlx5: DR, Remove protocol-specific flex_parser_3 definitions 



Remove MPLS specific fields from flex parser 3 layout.
Flex parser can be used for multiple protocols and should
not be hardcoded to a specific type.

Signed-off-by: default avatarMuhammad Sammar <muhammads@nvidia.com>
Signed-off-by: default avatarYevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent 704cfecd

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h

+7 −0
Original line number Diff line number Diff line
@@ -86,6 +86,13 @@ enum dr_ste_action_modify_type_l4 { 
	DR_STE_ACTION_MDFY_TYPE_L4_UDP	= 0x2,

};



enum {

	HDR_MPLS_OFFSET_LABEL	= 12,

	HDR_MPLS_OFFSET_EXP	= 9,

	HDR_MPLS_OFFSET_S_BOS	= 8,

	HDR_MPLS_OFFSET_TTL	= 0,

};



u16 mlx5dr_ste_conv_bit_to_byte_mask(u8 *bit_mask);



#define DR_STE_CTX_BUILDER(fname) \

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c

+19 −22
Original line number Diff line number Diff line
@@ -1248,32 +1248,29 @@ dr_ste_v0_build_tnl_mpls_tag(struct mlx5dr_match_param *value, 
			     u8 *tag)

{

	struct mlx5dr_match_misc2 *misc_2 = &value->misc2;

	u32 mpls_hdr;



	if (DR_STE_IS_OUTER_MPLS_OVER_GRE_SET(misc_2)) {

		DR_STE_SET_TAG(flex_parser_0, tag, parser_3_label,

			       misc_2, outer_first_mpls_over_gre_label);



		DR_STE_SET_TAG(flex_parser_0, tag, parser_3_exp,

			       misc_2, outer_first_mpls_over_gre_exp);



		DR_STE_SET_TAG(flex_parser_0, tag, parser_3_s_bos,

			       misc_2, outer_first_mpls_over_gre_s_bos);



		DR_STE_SET_TAG(flex_parser_0, tag, parser_3_ttl,

			       misc_2, outer_first_mpls_over_gre_ttl);

		mpls_hdr = misc_2->outer_first_mpls_over_gre_label << HDR_MPLS_OFFSET_LABEL;

		misc_2->outer_first_mpls_over_gre_label = 0;

		mpls_hdr |= misc_2->outer_first_mpls_over_gre_exp << HDR_MPLS_OFFSET_EXP;

		misc_2->outer_first_mpls_over_gre_exp = 0;

		mpls_hdr |= misc_2->outer_first_mpls_over_gre_s_bos << HDR_MPLS_OFFSET_S_BOS;

		misc_2->outer_first_mpls_over_gre_s_bos = 0;

		mpls_hdr |= misc_2->outer_first_mpls_over_gre_ttl << HDR_MPLS_OFFSET_TTL;

		misc_2->outer_first_mpls_over_gre_ttl = 0;

	} else {

		DR_STE_SET_TAG(flex_parser_0, tag, parser_3_label,

			       misc_2, outer_first_mpls_over_udp_label);



		DR_STE_SET_TAG(flex_parser_0, tag, parser_3_exp,

			       misc_2, outer_first_mpls_over_udp_exp);



		DR_STE_SET_TAG(flex_parser_0, tag, parser_3_s_bos,

			       misc_2, outer_first_mpls_over_udp_s_bos);



		DR_STE_SET_TAG(flex_parser_0, tag, parser_3_ttl,

			       misc_2, outer_first_mpls_over_udp_ttl);

		mpls_hdr = misc_2->outer_first_mpls_over_udp_label << HDR_MPLS_OFFSET_LABEL;

		misc_2->outer_first_mpls_over_udp_label = 0;

		mpls_hdr |= misc_2->outer_first_mpls_over_udp_exp << HDR_MPLS_OFFSET_EXP;

		misc_2->outer_first_mpls_over_udp_exp = 0;

		mpls_hdr |= misc_2->outer_first_mpls_over_udp_s_bos << HDR_MPLS_OFFSET_S_BOS;

		misc_2->outer_first_mpls_over_udp_s_bos = 0;

		mpls_hdr |= misc_2->outer_first_mpls_over_udp_ttl << HDR_MPLS_OFFSET_TTL;

		misc_2->outer_first_mpls_over_udp_ttl = 0;

	}



	MLX5_SET(ste_flex_parser_0, tag, flex_parser_3, mpls_hdr);

	return 0;

}

drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h

+1 −4
Original line number Diff line number Diff line
@@ -434,10 +434,7 @@ struct mlx5_ifc_ste_gre_bits { 
};



struct mlx5_ifc_ste_flex_parser_0_bits {

	u8         parser_3_label[0x14];

	u8         parser_3_exp[0x3];

	u8         parser_3_s_bos[0x1];

	u8         parser_3_ttl[0x8];

	u8         flex_parser_3[0x20];



	u8         flex_parser_2[0x20];