Commit 3216ceeb authored by Sebastian Reichel's avatar Sebastian Reichel Committed by Rob Herring
Browse files

dt-bindings: PCI: dwc: rockchip: Update for RK3588 



The PCIe 2.0 controllers on RK3588 need one additional clock,
one additional reset line and one for ranges entry.

Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230616170022.76107-4-sebastian.reichel@collabora.com


Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 74f02dd7

Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml

+13 −3
Original line number Diff line number Diff line
@@ -41,20 +41,24 @@ properties: 
      - const: config



  clocks:

    minItems: 5

    items:

      - description: AHB clock for PCIe master

      - description: AHB clock for PCIe slave

      - description: AHB clock for PCIe dbi

      - description: APB clock for PCIe

      - description: Auxiliary clock for PCIe

      - description: PIPE clock



  clock-names:

    minItems: 5

    items:

      - const: aclk_mst

      - const: aclk_slv

      - const: aclk_dbi

      - const: pclk

      - const: aux

      - const: pipe



  msi-map: true
@@ -70,13 +74,19 @@ properties: 
    maxItems: 1



  ranges:

    maxItems: 2

    minItems: 2

    maxItems: 3



  resets:

    maxItems: 1

    minItems: 1

    maxItems: 2



  reset-names:

    const: pipe

    oneOf:

      - const: pipe

      - items:

          - const: pwr

          - const: pipe



  vpcie3v3-supply: true