Commit 320eca62 authored by Wayne Lin's avatar Wayne Lin Committed by Alex Deucher
Browse files

drm/amd/display: Add otg vertical interrupt0 support in DCN1.0 



[Why & How]
On DCN1.0, need otg vertical line interrupt to get appropriate timing
to achieve specific feature request.

Add otg vertical interrupt0 support for registers which operation is
vertical sensitive.

Signed-off-by: default avatarWayne Lin <Wayne.Lin@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 11f1a553

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

+22 −0
Original line number Diff line number Diff line
@@ -662,6 +662,20 @@ static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev, 
		__func__);

}



static int amdgpu_dm_set_vline0_irq_state(struct amdgpu_device *adev,

					struct amdgpu_irq_src *source,

					unsigned int crtc_id,

					enum amdgpu_interrupt_state state)

{

	return dm_irq_state(

		adev,

		source,

		crtc_id,

		state,

		IRQ_TYPE_VLINE0,

		__func__);

}



static int amdgpu_dm_set_vupdate_irq_state(struct amdgpu_device *adev,

					   struct amdgpu_irq_src *source,

					   unsigned int crtc_id,
@@ -681,6 +695,11 @@ static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = { 
	.process = amdgpu_dm_irq_handler,

};



static const struct amdgpu_irq_src_funcs dm_vline0_irq_funcs = {

	.set = amdgpu_dm_set_vline0_irq_state,

	.process = amdgpu_dm_irq_handler,

};



static const struct amdgpu_irq_src_funcs dm_vupdate_irq_funcs = {

	.set = amdgpu_dm_set_vupdate_irq_state,

	.process = amdgpu_dm_irq_handler,
@@ -702,6 +721,9 @@ void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev) 
	adev->crtc_irq.num_types = adev->mode_info.num_crtc;

	adev->crtc_irq.funcs = &dm_crtc_irq_funcs;



	adev->vline0_irq.num_types = adev->mode_info.num_crtc;

	adev->vline0_irq.funcs = &dm_vline0_irq_funcs;



	adev->vupdate_irq.num_types = adev->mode_info.num_crtc;

	adev->vupdate_irq.funcs = &dm_vupdate_irq_funcs;

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

+31 −0
Original line number Diff line number Diff line
@@ -58,6 +58,18 @@ enum dc_irq_source to_dal_irq_source_dcn10( 
		return DC_IRQ_SOURCE_VBLANK5;

	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:

		return DC_IRQ_SOURCE_VBLANK6;

	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:

		return DC_IRQ_SOURCE_DC1_VLINE0;

	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:

		return DC_IRQ_SOURCE_DC2_VLINE0;

	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:

		return DC_IRQ_SOURCE_DC3_VLINE0;

	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:

		return DC_IRQ_SOURCE_DC4_VLINE0;

	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:

		return DC_IRQ_SOURCE_DC5_VLINE0;

	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:

		return DC_IRQ_SOURCE_DC6_VLINE0;

	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:

		return DC_IRQ_SOURCE_VUPDATE1;

	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
@@ -167,6 +179,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = { 
	.ack = NULL

};



static const struct irq_source_info_funcs vline0_irq_info_funcs = {

	.set = NULL,

	.ack = NULL

};



static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {

	.set = NULL,

	.ack = NULL
@@ -241,6 +258,14 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { 
		.funcs = &vblank_irq_info_funcs\

	}



#define vline0_int_entry(reg_num)\

	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\

		IRQ_REG_ENTRY(OTG, reg_num,\

			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\

			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\

		.funcs = &vline0_irq_info_funcs\

	}



#define dummy_irq_entry() \

	{\

		.funcs = &dummy_irq_info_funcs\
@@ -349,6 +374,12 @@ irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = { 
	vblank_int_entry(3),

	vblank_int_entry(4),

	vblank_int_entry(5),

	vline0_int_entry(0),

	vline0_int_entry(1),

	vline0_int_entry(2),

	vline0_int_entry(3),

	vline0_int_entry(4),

	vline0_int_entry(5),

};



static const struct irq_service_funcs irq_service_funcs_dcn10 = {

drivers/gpu/drm/amd/display/dc/irq_types.h

+1 −0
Original line number Diff line number Diff line
@@ -160,6 +160,7 @@ enum irq_type 
	IRQ_TYPE_PFLIP = DC_IRQ_SOURCE_PFLIP1,

	IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1,

	IRQ_TYPE_VBLANK = DC_IRQ_SOURCE_VBLANK1,

	IRQ_TYPE_VLINE0 = DC_IRQ_SOURCE_DC1_VLINE0,

};



#define DAL_VALID_IRQ_SRC_NUM(src) \