Commit 31dc3095 authored by LeoLiu-oc's avatar LeoLiu-oc Committed by Zheng Zengkai
Browse files

rtc: Fix set RTC time delay 500ms on some Zhaoxin SOCs

zhaoxin inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I40QDN


CVE: NA

----------------------------------------------------------------

When the RTC divider is changed from reset to an operating time base,
the first update cycle should be 500ms later. But on some Zhaoxin SOCs,
this first update cycle is one second later.
So set RTC time on these Zhaoxin SOCs will causing 500ms delay.
Skip setup RTC divider on these SOCs in mc146818_set_time to fix it.

Signed-off-by: default avatarLeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
Reviewed-by: default avatarXiongfeng Wang <wangxiongfeng2@huawei.com>
parent 219d1d28
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+23 −3
Original line number Diff line number Diff line
@@ -8,6 +8,22 @@
#include <linux/acpi.h>
#endif

#ifdef CONFIG_X86
static inline bool follow_mc146818_divider_reset(void)
{
	if ((boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR ||
		boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) &&
		(boot_cpu_data.x86 <= 7 && boot_cpu_data.x86_model <= 59))
		return false;
	return true;
}
#else
static inline bool follow_mc146818_divider_reset(void)
{
	return true;
}
#endif

/*
 * Returns true if a clock update is in progress
 */
@@ -171,8 +187,11 @@ int mc146818_set_time(struct rtc_time *time)

	save_control = CMOS_READ(RTC_CONTROL);
	CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
	if (follow_mc146818_divider_reset()) {
		save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
		CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
	}


#ifdef CONFIG_MACH_DECSTATION
	CMOS_WRITE(real_yrs, RTC_DEC_YEAR);
@@ -190,6 +209,7 @@ int mc146818_set_time(struct rtc_time *time)
#endif

	CMOS_WRITE(save_control, RTC_CONTROL);
	if (follow_mc146818_divider_reset())
		CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);

	spin_unlock_irqrestore(&rtc_lock, flags);