Loading drivers/mmc/host/Kconfig +1 −1 Original line number Diff line number Diff line Loading @@ -508,7 +508,7 @@ config MMC_OMAP_HS config MMC_WBSD tristate "Winbond W83L51xD SD/MMC Card Interface support" depends on ISA_DMA_API depends on ISA_DMA_API && !M68K help This selects the Winbond(R) W83L51xD Secure digital and Multimedia card Interface. Loading drivers/mmc/host/sdhci-esdhc-imx.c +16 −0 Original line number Diff line number Diff line Loading @@ -1187,6 +1187,7 @@ static void esdhc_reset_tuning(struct sdhci_host *host) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); u32 ctrl; int ret; /* Reset the tuning circuit */ if (esdhc_is_usdhc(imx_data)) { Loading @@ -1199,7 +1200,22 @@ static void esdhc_reset_tuning(struct sdhci_host *host) } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE; writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */ ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50); if (ret == -ETIMEDOUT) dev_warn(mmc_dev(host->mmc), "Warning! clear execute tuning bit failed\n"); /* * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the * usdhc IP internal logic flag execute_tuning_with_clr_buf, which * will finally make sure the normal data transfer logic correct. */ ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); ctrl |= SDHCI_INT_DATA_AVAIL; writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); } } } Loading Loading
drivers/mmc/host/Kconfig +1 −1 Original line number Diff line number Diff line Loading @@ -508,7 +508,7 @@ config MMC_OMAP_HS config MMC_WBSD tristate "Winbond W83L51xD SD/MMC Card Interface support" depends on ISA_DMA_API depends on ISA_DMA_API && !M68K help This selects the Winbond(R) W83L51xD Secure digital and Multimedia card Interface. Loading
drivers/mmc/host/sdhci-esdhc-imx.c +16 −0 Original line number Diff line number Diff line Loading @@ -1187,6 +1187,7 @@ static void esdhc_reset_tuning(struct sdhci_host *host) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); u32 ctrl; int ret; /* Reset the tuning circuit */ if (esdhc_is_usdhc(imx_data)) { Loading @@ -1199,7 +1200,22 @@ static void esdhc_reset_tuning(struct sdhci_host *host) } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE; writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */ ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50); if (ret == -ETIMEDOUT) dev_warn(mmc_dev(host->mmc), "Warning! clear execute tuning bit failed\n"); /* * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the * usdhc IP internal logic flag execute_tuning_with_clr_buf, which * will finally make sure the normal data transfer logic correct. */ ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); ctrl |= SDHCI_INT_DATA_AVAIL; writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); } } } Loading