Commit 319e568b authored by Shenming Lu's avatar Shenming Lu Committed by Zheng Zengkai
Browse files

irqchip/gic-v4.1: Reduce the delay when polling GICR_VPENDBASER.Dirty 

virt inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I40TDK


CVE: NA

---------------------------

The 10us delay of the poll on the GICR_VPENDBASER.Dirty bit is too
high, which might greatly affect the total scheduling latency of a
vCPU in our measurement. So we reduce it to 1 to lessen the impact.

Signed-off-by: default avatarShenming Lu <lushenming@huawei.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20201128141857.983-2-lushenming@huawei.com


Reviewed-by: default avatarKeqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 19339c51

drivers/irqchip/irq-gic-v3-its.c

+1 −1
Original line number Diff line number Diff line
@@ -3808,7 +3808,7 @@ static void its_wait_vpt_parse_complete(void) 
	WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER,

						       val,

						       !(val & GICR_VPENDBASER_Dirty),

						       10, 500));

						       1, 500));

}



static void its_vpe_schedule(struct its_vpe *vpe)