Commit 319aeaf6 authored by Rob Herring's avatar Rob Herring Committed by Sudeep Holla
Browse files

arm: dts: vexpress: Fix motherboard bus 'interrupt-map' 

Commit 078fb7aa ("arm: dts: vexpress: Fix addressing issues with
'motherboard-bus' nodes") broke booting on a couple of 32-bit VExpress
boards. The problem is #address-cells size changed, but interrupt-map
was not updated. This results in the timer interrupt (and all the
other motherboard interrupts) not getting mapped.

As the 'interrupt-map' properties are all just duplicates across boards,
just move them into vexpress-v2m.dtsi and vexpress-v2m-rs1.dtsi.
Strictly speaking, 'interrupt-map' is dependent on the parent
interrupt controller, but it's not likely we'll ever have a different
parent than GICv2 on these old platforms. If there was one,
'interrupt-map' can still be overridden.

Link: https://lore.kernel.org/r/20210924214221.1877686-1-robh@kernel.org


Fixes: 078fb7aa ("arm: dts: vexpress: Fix addressing issues with 'motherboard-bus' nodes")
Cc: Guillaume Tucker <guillaume.tucker@collabora.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Reported-by: default avatarReported-by: "kernelci.org bot" <bot@kernelci.org>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent 078fb7aa

arch/arm/boot/dts/vexpress-v2m-rs1.dtsi

+47 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT

 * CHANGES TO vexpress-v2m.dtsi!

 */

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	v2m_fixed_3v3: fixed-regulator-0 {
@@ -105,6 +106,52 @@ 
		#address-cells = <1>;

		#size-cells = <1>;



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 63>;

		interrupt-map = <0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,

				<0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,

				<0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,

				<0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,

				<0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,

				<0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,

				<0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,

				<0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,

				<0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,

				<0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,

				<0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

				<0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,

				<0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,

				<0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,

				<0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,

				<0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,

				<0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,

				<0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,

				<0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,

				<0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,

				<0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,

				<0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,

				<0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,

				<0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,

				<0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

				<0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,

				<0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

				<0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,

				<0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,

				<0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,

				<0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

				<0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,

				<0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

				<0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

				<0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

				<0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,

				<0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

				<0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,

				<0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,

				<0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

				<0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

				<0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

				<0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;



		motherboard-bus@8000000 {

			arm,hbi = <0x190>;

			arm,vexpress,site = <0>;

arch/arm/boot/dts/vexpress-v2m.dtsi

+47 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT

 * CHANGES TO vexpress-v2m-rs1.dtsi!

 */

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	bus@40000000 {
@@ -26,6 +27,52 @@ 
		ranges = <0x40000000 0x40000000 0x10000000>,

			 <0x10000000 0x10000000 0x00020000>;



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 63>;

		interrupt-map = <0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,

				<0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,

				<0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,

				<0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,

				<0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,

				<0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,

				<0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,

				<0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,

				<0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,

				<0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,

				<0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

				<0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,

				<0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,

				<0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,

				<0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,

				<0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,

				<0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,

				<0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,

				<0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,

				<0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,

				<0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,

				<0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,

				<0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,

				<0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,

				<0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

				<0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,

				<0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

				<0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,

				<0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,

				<0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,

				<0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

				<0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,

				<0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

				<0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

				<0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

				<0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,

				<0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

				<0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,

				<0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,

				<0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

				<0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

				<0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

				<0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;



		motherboard-bus@40000000 {

			arm,hbi = <0x190>;

			arm,vexpress,site = <0>;

arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts

+0 −46
Original line number Diff line number Diff line
@@ -238,52 +238,6 @@ 


	bus@8000000 {

		ranges = <0x8000000 0 0x8000000 0x18000000>;



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 63>;

		interrupt-map = <0 0  0 &gic 0  0 4>,

				<0 0  1 &gic 0  1 4>,

				<0 0  2 &gic 0  2 4>,

				<0 0  3 &gic 0  3 4>,

				<0 0  4 &gic 0  4 4>,

				<0 0  5 &gic 0  5 4>,

				<0 0  6 &gic 0  6 4>,

				<0 0  7 &gic 0  7 4>,

				<0 0  8 &gic 0  8 4>,

				<0 0  9 &gic 0  9 4>,

				<0 0 10 &gic 0 10 4>,

				<0 0 11 &gic 0 11 4>,

				<0 0 12 &gic 0 12 4>,

				<0 0 13 &gic 0 13 4>,

				<0 0 14 &gic 0 14 4>,

				<0 0 15 &gic 0 15 4>,

				<0 0 16 &gic 0 16 4>,

				<0 0 17 &gic 0 17 4>,

				<0 0 18 &gic 0 18 4>,

				<0 0 19 &gic 0 19 4>,

				<0 0 20 &gic 0 20 4>,

				<0 0 21 &gic 0 21 4>,

				<0 0 22 &gic 0 22 4>,

				<0 0 23 &gic 0 23 4>,

				<0 0 24 &gic 0 24 4>,

				<0 0 25 &gic 0 25 4>,

				<0 0 26 &gic 0 26 4>,

				<0 0 27 &gic 0 27 4>,

				<0 0 28 &gic 0 28 4>,

				<0 0 29 &gic 0 29 4>,

				<0 0 30 &gic 0 30 4>,

				<0 0 31 &gic 0 31 4>,

				<0 0 32 &gic 0 32 4>,

				<0 0 33 &gic 0 33 4>,

				<0 0 34 &gic 0 34 4>,

				<0 0 35 &gic 0 35 4>,

				<0 0 36 &gic 0 36 4>,

				<0 0 37 &gic 0 37 4>,

				<0 0 38 &gic 0 38 4>,

				<0 0 39 &gic 0 39 4>,

				<0 0 40 &gic 0 40 4>,

				<0 0 41 &gic 0 41 4>,

				<0 0 42 &gic 0 42 4>;

	};



	site2: hsb@40000000 {

arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

+0 −46
Original line number Diff line number Diff line
@@ -610,52 +610,6 @@ 


	smb: bus@8000000 {

		ranges = <0x8000000 0 0x8000000 0x18000000>;



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 63>;

		interrupt-map = <0 0  0 &gic 0  0 4>,

				<0 0  1 &gic 0  1 4>,

				<0 0  2 &gic 0  2 4>,

				<0 0  3 &gic 0  3 4>,

				<0 0  4 &gic 0  4 4>,

				<0 0  5 &gic 0  5 4>,

				<0 0  6 &gic 0  6 4>,

				<0 0  7 &gic 0  7 4>,

				<0 0  8 &gic 0  8 4>,

				<0 0  9 &gic 0  9 4>,

				<0 0 10 &gic 0 10 4>,

				<0 0 11 &gic 0 11 4>,

				<0 0 12 &gic 0 12 4>,

				<0 0 13 &gic 0 13 4>,

				<0 0 14 &gic 0 14 4>,

				<0 0 15 &gic 0 15 4>,

				<0 0 16 &gic 0 16 4>,

				<0 0 17 &gic 0 17 4>,

				<0 0 18 &gic 0 18 4>,

				<0 0 19 &gic 0 19 4>,

				<0 0 20 &gic 0 20 4>,

				<0 0 21 &gic 0 21 4>,

				<0 0 22 &gic 0 22 4>,

				<0 0 23 &gic 0 23 4>,

				<0 0 24 &gic 0 24 4>,

				<0 0 25 &gic 0 25 4>,

				<0 0 26 &gic 0 26 4>,

				<0 0 27 &gic 0 27 4>,

				<0 0 28 &gic 0 28 4>,

				<0 0 29 &gic 0 29 4>,

				<0 0 30 &gic 0 30 4>,

				<0 0 31 &gic 0 31 4>,

				<0 0 32 &gic 0 32 4>,

				<0 0 33 &gic 0 33 4>,

				<0 0 34 &gic 0 34 4>,

				<0 0 35 &gic 0 35 4>,

				<0 0 36 &gic 0 36 4>,

				<0 0 37 &gic 0 37 4>,

				<0 0 38 &gic 0 38 4>,

				<0 0 39 &gic 0 39 4>,

				<0 0 40 &gic 0 40 4>,

				<0 0 41 &gic 0 41 4>,

				<0 0 42 &gic 0 42 4>;

	};



	site2: hsb@40000000 {

arch/arm/boot/dts/vexpress-v2p-ca5s.dts

+0 −46
Original line number Diff line number Diff line
@@ -208,52 +208,6 @@ 


	smb: bus@8000000 {

		ranges = <0 0x8000000 0x18000000>;



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 63>;

		interrupt-map = <0 0  0 &gic 0  0 4>,

				<0 0  1 &gic 0  1 4>,

				<0 0  2 &gic 0  2 4>,

				<0 0  3 &gic 0  3 4>,

				<0 0  4 &gic 0  4 4>,

				<0 0  5 &gic 0  5 4>,

				<0 0  6 &gic 0  6 4>,

				<0 0  7 &gic 0  7 4>,

				<0 0  8 &gic 0  8 4>,

				<0 0  9 &gic 0  9 4>,

				<0 0 10 &gic 0 10 4>,

				<0 0 11 &gic 0 11 4>,

				<0 0 12 &gic 0 12 4>,

				<0 0 13 &gic 0 13 4>,

				<0 0 14 &gic 0 14 4>,

				<0 0 15 &gic 0 15 4>,

				<0 0 16 &gic 0 16 4>,

				<0 0 17 &gic 0 17 4>,

				<0 0 18 &gic 0 18 4>,

				<0 0 19 &gic 0 19 4>,

				<0 0 20 &gic 0 20 4>,

				<0 0 21 &gic 0 21 4>,

				<0 0 22 &gic 0 22 4>,

				<0 0 23 &gic 0 23 4>,

				<0 0 24 &gic 0 24 4>,

				<0 0 25 &gic 0 25 4>,

				<0 0 26 &gic 0 26 4>,

				<0 0 27 &gic 0 27 4>,

				<0 0 28 &gic 0 28 4>,

				<0 0 29 &gic 0 29 4>,

				<0 0 30 &gic 0 30 4>,

				<0 0 31 &gic 0 31 4>,

				<0 0 32 &gic 0 32 4>,

				<0 0 33 &gic 0 33 4>,

				<0 0 34 &gic 0 34 4>,

				<0 0 35 &gic 0 35 4>,

				<0 0 36 &gic 0 36 4>,

				<0 0 37 &gic 0 37 4>,

				<0 0 38 &gic 0 38 4>,

				<0 0 39 &gic 0 39 4>,

				<0 0 40 &gic 0 40 4>,

				<0 0 41 &gic 0 41 4>,

				<0 0 42 &gic 0 42 4>;

	};



	site2: hsb@40000000 {