Commit 319568d7 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Updates SubVP and SubVP DRR cases 



[Description]
- For any DRR cases in SubVP, don't lock for VSYNC flips
- For DCN32/321 use FW to do DRR manual trigger programming
- Add bit in SubVP cmd to indicate if the SubVP pipe is DRR

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2ce0b218

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

+17 −0
Original line number Diff line number Diff line
@@ -270,6 +270,23 @@ void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal 
	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);

}



void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)

{

	union dmub_rb_cmd cmd = { 0 };



	cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;

	// TODO: Uncomment once FW headers are promoted

	//cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;

	cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;



	cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);



	// Send the command to the DMCUB.

	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);

	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);

	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);

}



static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)

{

	uint8_t pipes = 0;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

+1 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ void dc_dmub_trace_event_control(struct dc *dc, bool enable); 


void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max);



void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst);

bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct dc_state *context);



void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

+2 −5
Original line number Diff line number Diff line
@@ -424,7 +424,6 @@ void dcn32_subvp_pipe_control_lock(struct dc *dc, 
	unsigned int i = 0;

	bool subvp_immediate_flip = false;

	bool subvp_in_use = false;

	bool drr_pipe = false;

	struct pipe_ctx *pipe;



	for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -440,12 +439,10 @@ void dcn32_subvp_pipe_control_lock(struct dc *dc, 
		if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN &&

				top_pipe_to_program->plane_state->flip_immediate)

			subvp_immediate_flip = true;

		else if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_NONE &&

				top_pipe_to_program->stream->ignore_msa_timing_param)

			drr_pipe = true;

	}



	if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip || drr_pipe)) || (!subvp_in_use && subvp_prev_use)) {

	// Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.

	if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) {

		union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };



		if (!lock) {

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c

+62 −1
Original line number Diff line number Diff line
@@ -26,9 +26,11 @@ 
#include "dcn32_optc.h"



#include "dcn30/dcn30_optc.h"

#include "dcn31/dcn31_optc.h"

#include "reg_helper.h"

#include "dc.h"

#include "dcn_calc_math.h"

#include "dc_dmub_srv.h"



#define REG(reg)\

	optc1->tg_regs->reg
@@ -188,6 +190,65 @@ static void optc32_set_odm_bypass(struct timing_generator *optc, 
	optc1->opp_count = 1;

}



void optc32_setup_manual_trigger(struct timing_generator *optc)

{

	struct optc *optc1 = DCN10TG_FROM_TG(optc);

	struct dc *dc = optc->ctx->dc;



	if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)

		dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);

	else {

		/*

		 * MIN_MASK_EN is gone and MASK is now always enabled.

		 *

		 * To get it to it work with manual trigger we need to make sure

		 * we program the correct bit.

		 */

		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

				OTG_V_TOTAL_MIN_SEL, 1,

				OTG_V_TOTAL_MAX_SEL, 1,

				OTG_FORCE_LOCK_ON_EVENT, 0,

				OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */



		// Setup manual flow control for EOF via TRIG_A

		optc->funcs->setup_manual_trigger(optc);

	}

}



void optc32_set_drr(

	struct timing_generator *optc,

	const struct drr_params *params)

{

	struct optc *optc1 = DCN10TG_FROM_TG(optc);



	if (params != NULL &&

		params->vertical_total_max > 0 &&

		params->vertical_total_min > 0) {



		if (params->vertical_total_mid != 0) {



			REG_SET(OTG_V_TOTAL_MID, 0,

				OTG_V_TOTAL_MID, params->vertical_total_mid - 1);



			REG_UPDATE_2(OTG_V_TOTAL_CONTROL,

					OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,

					OTG_VTOTAL_MID_FRAME_NUM,

					(uint8_t)params->vertical_total_mid_frame_num);



		}



		optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);

		optc32_setup_manual_trigger(optc);

	} else {

		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

				OTG_SET_V_TOTAL_MIN_MASK, 0,

				OTG_V_TOTAL_MIN_SEL, 0,

				OTG_V_TOTAL_MAX_SEL, 0,

				OTG_FORCE_LOCK_ON_EVENT, 0);



		optc->funcs->set_vtotal_min_max(optc, 0, 0);

	}

}



static struct timing_generator_funcs dcn32_tg_funcs = {

		.validate_timing = optc1_validate_timing,
@@ -221,7 +282,7 @@ static struct timing_generator_funcs dcn32_tg_funcs = { 
		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,

		.enable_optc_clock = optc1_enable_optc_clock,

		.set_vrr_m_const = optc3_set_vrr_m_const,

		.set_drr = optc1_set_drr,

		.set_drr = optc31_set_drr, // TODO: Update to optc32_set_drr once FW headers are promoted

		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,

		.set_vtotal_min_max = optc3_set_vtotal_min_max,

		.set_static_screen_control = optc1_set_static_screen_control,