Commit 314c7629 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Increase timeout threshold for DMCUB reset 



[Why]
If we're backdoor loading the DMCUB performs more work than just
the PHY reset so we can end up resetting before the cleanup has fully
finished.

[How]
Increase timeout, add udelay between spins to guarantee a minimum.

Reviewed-by: default avatarRoy Chan <roy.chan@amd.com>
Reviewed-by: default avatarEric Yang <Eric.Yang2@amd.com>
Acked-by: default avatarAnson Jacob <Anson.Jacob@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 19c618e6

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

+5 −5
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ static inline void dmub_dcn31_translate_addr(const union dmub_addr *addr_in, 
void dmub_dcn31_reset(struct dmub_srv *dmub)

{

	union dmub_gpint_data_register cmd;

	const uint32_t timeout = 30;

	const uint32_t timeout = 100;

	uint32_t in_reset, scratch, i;



	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
@@ -98,21 +98,21 @@ void dmub_dcn31_reset(struct dmub_srv *dmub) 
		/**

		 * Timeout covers both the ACK and the wait

		 * for remaining work to finish.

		 *

		 * This is mostly bound by the PHY disable sequence.

		 * Each register check will be greater than 1us, so

		 * don't bother using udelay.

		 */



		for (i = 0; i < timeout; ++i) {

			if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))

				break;



			udelay(1);

		}



		for (i = 0; i < timeout; ++i) {

			scratch = dmub->hw_funcs.get_gpint_response(dmub);

			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)

				break;



			udelay(1);

		}



		/* Force reset in case we timed out, DMCUB is likely hung. */