Commit 312817a3 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Only save and restore fences for UMS 



With KMS, we can simply relinquish the fence when we idle the GPU and
reassign it upon first use.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent c6642782

drivers/gpu/drm/i915/i915_gem.c

+15 −10
Original line number Diff line number Diff line
@@ -1905,11 +1905,22 @@ static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, 
	}

}



static void i915_gem_reset_fences(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int i;



	for (i = 0; i < 16; i++) {

		struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];

		if (reg->obj)

			i915_gem_clear_fence_reg(reg->obj);

	}

}



void i915_gem_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_gem_object *obj;

	int i;



	i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring);

	i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring);
@@ -1940,15 +1951,7 @@ void i915_gem_reset(struct drm_device *dev) 
	}



	/* The fence registers are invalidated so clear them out */

	for (i = 0; i < 16; i++) {

		struct drm_i915_fence_reg *reg;



		reg = &dev_priv->fence_regs[i];

		if (!reg->obj)

			continue;



		i915_gem_clear_fence_reg(reg->obj);

	}

	i915_gem_reset_fences(dev);

}



/**
@@ -4706,6 +4709,8 @@ i915_gem_idle(struct drm_device *dev) 
		}

	}



	i915_gem_reset_fences(dev);



	/* Hack!  Don't let anybody do execbuf while we don't control the chip.

	 * We need to replace this with a semaphore, or something.

	 * And not confound mm.suspended!

drivers/gpu/drm/i915/i915_suspend.c

+46 −43
Original line number Diff line number Diff line
@@ -235,6 +235,7 @@ static void i915_restore_vga(struct drm_device *dev) 
static void i915_save_modeset_reg(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int i;



	if (drm_core_check_feature(dev, DRIVER_MODESET))

		return;
@@ -367,6 +368,28 @@ static void i915_save_modeset_reg(struct drm_device *dev) 
	}

	i915_save_palette(dev, PIPE_B);

	dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);



	/* Fences */

	switch (INTEL_INFO(dev)->gen) {

	case 6:

		for (i = 0; i < 16; i++)

			dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));

		break;

	case 5:

	case 4:

		for (i = 0; i < 16; i++)

			dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));

		break;

	case 3:

		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))

			for (i = 0; i < 8; i++)

				dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));

	case 2:

		for (i = 0; i < 8; i++)

			dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));

		break;

	}



	return;

}
@@ -375,10 +398,33 @@ static void i915_restore_modeset_reg(struct drm_device *dev) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	int dpll_a_reg, fpa0_reg, fpa1_reg;

	int dpll_b_reg, fpb0_reg, fpb1_reg;

	int i;



	if (drm_core_check_feature(dev, DRIVER_MODESET))

		return;



	/* Fences */

	switch (INTEL_INFO(dev)->gen) {

	case 6:

		for (i = 0; i < 16; i++)

			I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);

		break;

	case 5:

	case 4:

		for (i = 0; i < 16; i++)

			I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);

		break;

	case 3:

	case 2:

		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))

			for (i = 0; i < 8; i++)

				I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);

		for (i = 0; i < 8; i++)

			I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);

		break;

	}





	if (HAS_PCH_SPLIT(dev)) {

		dpll_a_reg = PCH_DPLL_A;

		dpll_b_reg = PCH_DPLL_B;
@@ -788,28 +834,6 @@ int i915_save_state(struct drm_device *dev) 
	for (i = 0; i < 3; i++)

		dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));



	/* Fences */

	switch (INTEL_INFO(dev)->gen) {

	case 6:

		for (i = 0; i < 16; i++)

			dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));

		break;

	case 5:

	case 4:

		for (i = 0; i < 16; i++)

			dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));

		break;

	case 3:

		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))

			for (i = 0; i < 8; i++)

				dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));

	case 2:

		for (i = 0; i < 8; i++)

			dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));

		break;



	}



	return 0;

}
@@ -823,27 +847,6 @@ int i915_restore_state(struct drm_device *dev) 
	/* Hardware status page */

	I915_WRITE(HWS_PGA, dev_priv->saveHWS);



	/* Fences */

	switch (INTEL_INFO(dev)->gen) {

	case 6:

		for (i = 0; i < 16; i++)

			I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);

		break;

	case 5:

	case 4:

		for (i = 0; i < 16; i++)

			I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);

		break;

	case 3:

	case 2:

		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))

			for (i = 0; i < 8; i++)

				I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);

		for (i = 0; i < 8; i++)

			I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);

		break;

	}



	i915_restore_display(dev);



	/* Interrupt state */