Unverified Commit 3116e748 authored by Mark Brown's avatar Mark Brown
Browse files

Merge remote-tracking branches 'asoc/topic/mc13783', 'asoc/topic/msm8916',... 

Merge remote-tracking branches 'asoc/topic/mc13783', 'asoc/topic/msm8916', 'asoc/topic/mt8173', 'asoc/topic/mtk' and 'asoc/topic/nau8540' into asoc-next
parents 87c90ac0 33953d85 42e193cd d6e2c4ff 7f12a563 fe83b1b7

Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt

+128 −138
Original line number Diff line number Diff line
@@ -2,153 +2,143 @@ Mediatek AFE PCM controller for mt2701 


Required properties:

- compatible = "mediatek,mt2701-audio";

- reg: register location and size

- interrupts: should contain AFE and ASYS interrupts

- interrupt-names: should be "afe" and "asys"

- power-domains: should define the power domain

- clocks: Must contain an entry for each entry in clock-names

  See ../clocks/clock-bindings.txt for details

- clock-names: should have these clock names:

		"infra_sys_audio_clk",

		"top_audio_mux1_sel",

		"top_audio_mux2_sel",

		"top_audio_mux1_div",

		"top_audio_mux2_div",

		"top_audio_48k_timing",

		"top_audio_44k_timing",

		"top_audpll_mux_sel",

		"top_apll_sel",

		"top_aud1_pll_98M",

		"top_aud2_pll_90M",

		"top_hadds2_pll_98M",

		"top_hadds2_pll_294M",

		"top_audpll",

		"top_audpll_d4",

		"top_audpll_d8",

		"top_audpll_d16",

		"top_audpll_d24",

		"top_audintbus_sel",

		"clk_26m",

		"top_syspll1_d4",

		"top_aud_k1_src_sel",

		"top_aud_k2_src_sel",

		"top_aud_k3_src_sel",

		"top_aud_k4_src_sel",

		"top_aud_k5_src_sel",

		"top_aud_k6_src_sel",

		"top_aud_k1_src_div",

		"top_aud_k2_src_div",

		"top_aud_k3_src_div",

		"top_aud_k4_src_div",

		"top_aud_k5_src_div",

		"top_aud_k6_src_div",

		"top_aud_i2s1_mclk",

		"top_aud_i2s2_mclk",

		"top_aud_i2s3_mclk",

		"top_aud_i2s4_mclk",

		"top_aud_i2s5_mclk",

		"top_aud_i2s6_mclk",

		"top_asm_m_sel",

		"top_asm_h_sel",

		"top_univpll2_d4",

		"top_univpll2_d2",

		"top_syspll_d5";

		"top_audio_a1sys_hp",

		"top_audio_a2sys_hp",

		"i2s0_src_sel",

		"i2s1_src_sel",

		"i2s2_src_sel",

		"i2s3_src_sel",

		"i2s0_src_div",

		"i2s1_src_div",

		"i2s2_src_div",

		"i2s3_src_div",

		"i2s0_mclk_en",

		"i2s1_mclk_en",

		"i2s2_mclk_en",

		"i2s3_mclk_en",

		"i2so0_hop_ck",

		"i2so1_hop_ck",

		"i2so2_hop_ck",

		"i2so3_hop_ck",

		"i2si0_hop_ck",

		"i2si1_hop_ck",

		"i2si2_hop_ck",

		"i2si3_hop_ck",

		"asrc0_out_ck",

		"asrc1_out_ck",

		"asrc2_out_ck",

		"asrc3_out_ck",

		"audio_afe_pd",

		"audio_afe_conn_pd",

		"audio_a1sys_pd",

		"audio_a2sys_pd",

		"audio_mrgif_pd";

- assigned-clocks: list of input clocks and dividers for the audio system.

		   See ../clocks/clock-bindings.txt for details.

- assigned-clocks-parents: parent of input clocks of assigned clocks.

- assigned-clock-rates: list of clock frequencies of assigned clocks.



Must be a subnode of MediaTek audsys device tree node.

See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.



Example:



	afe: mt2701-afe-pcm@11220000 {

	audsys: audio-subsystem@11220000 {

		compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";

		...



		afe: audio-controller {

			compatible = "mediatek,mt2701-audio";

		reg = <0 0x11220000 0 0x2000>,

		      <0 0x112A0000 0 0x20000>;

			interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,

				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;

			interrupt-names	= "afe", "asys";

			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;



			clocks = <&infracfg CLK_INFRA_AUDIO>,

				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,

				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,

			 <&topckgen CLK_TOP_AUD_MUX1_DIV>,

			 <&topckgen CLK_TOP_AUD_MUX2_DIV>,

				 <&topckgen CLK_TOP_AUD_48K_TIMING>,

				 <&topckgen CLK_TOP_AUD_44K_TIMING>,

			 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,

			 <&topckgen CLK_TOP_APLL_SEL>,

			 <&topckgen CLK_TOP_AUD1PLL_98M>,

			 <&topckgen CLK_TOP_AUD2PLL_90M>,

			 <&topckgen CLK_TOP_HADDS2PLL_98M>,

			 <&topckgen CLK_TOP_HADDS2PLL_294M>,

			 <&topckgen CLK_TOP_AUDPLL>,

			 <&topckgen CLK_TOP_AUDPLL_D4>,

			 <&topckgen CLK_TOP_AUDPLL_D8>,

			 <&topckgen CLK_TOP_AUDPLL_D16>,

			 <&topckgen CLK_TOP_AUDPLL_D24>,

			 <&topckgen CLK_TOP_AUDINTBUS_SEL>,

			 <&clk26m>,

			 <&topckgen CLK_TOP_SYSPLL1_D4>,

				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,

				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,

				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,

				 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,

			 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,

			 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,

				 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,

				 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,

				 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,

				 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,

			 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,

			 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,

				 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,

				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,

				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,

				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,

			 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,

			 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,

			 <&topckgen CLK_TOP_ASM_M_SEL>,

			 <&topckgen CLK_TOP_ASM_H_SEL>,

			 <&topckgen CLK_TOP_UNIVPLL2_D4>,

			 <&topckgen CLK_TOP_UNIVPLL2_D2>,

			 <&topckgen CLK_TOP_SYSPLL_D5>;

				 <&audsys CLK_AUD_I2SO1>,

				 <&audsys CLK_AUD_I2SO2>,

				 <&audsys CLK_AUD_I2SO3>,

				 <&audsys CLK_AUD_I2SO4>,

				 <&audsys CLK_AUD_I2SIN1>,

				 <&audsys CLK_AUD_I2SIN2>,

				 <&audsys CLK_AUD_I2SIN3>,

				 <&audsys CLK_AUD_I2SIN4>,

				 <&audsys CLK_AUD_ASRCO1>,

				 <&audsys CLK_AUD_ASRCO2>,

				 <&audsys CLK_AUD_ASRCO3>,

				 <&audsys CLK_AUD_ASRCO4>,

				 <&audsys CLK_AUD_AFE>,

				 <&audsys CLK_AUD_AFE_CONN>,

				 <&audsys CLK_AUD_A1SYS>,

				 <&audsys CLK_AUD_A2SYS>,

				 <&audsys CLK_AUD_AFE_MRGIF>;



			clock-names = "infra_sys_audio_clk",

				      "top_audio_mux1_sel",

				      "top_audio_mux2_sel",

			      "top_audio_mux1_div",

			      "top_audio_mux2_div",

			      "top_audio_48k_timing",

			      "top_audio_44k_timing",

			      "top_audpll_mux_sel",

			      "top_apll_sel",

			      "top_aud1_pll_98M",

			      "top_aud2_pll_90M",

			      "top_hadds2_pll_98M",

			      "top_hadds2_pll_294M",

			      "top_audpll",

			      "top_audpll_d4",

			      "top_audpll_d8",

			      "top_audpll_d16",

			      "top_audpll_d24",

			      "top_audintbus_sel",

			      "clk_26m",

			      "top_syspll1_d4",

			      "top_aud_k1_src_sel",

			      "top_aud_k2_src_sel",

			      "top_aud_k3_src_sel",

			      "top_aud_k4_src_sel",

			      "top_aud_k5_src_sel",

			      "top_aud_k6_src_sel",

			      "top_aud_k1_src_div",

			      "top_aud_k2_src_div",

			      "top_aud_k3_src_div",

			      "top_aud_k4_src_div",

			      "top_aud_k5_src_div",

			      "top_aud_k6_src_div",

			      "top_aud_i2s1_mclk",

			      "top_aud_i2s2_mclk",

			      "top_aud_i2s3_mclk",

			      "top_aud_i2s4_mclk",

			      "top_aud_i2s5_mclk",

			      "top_aud_i2s6_mclk",

			      "top_asm_m_sel",

			      "top_asm_h_sel",

			      "top_univpll2_d4",

			      "top_univpll2_d2",

			      "top_syspll_d5";

				      "top_audio_a1sys_hp",

				      "top_audio_a2sys_hp",

				      "i2s0_src_sel",

				      "i2s1_src_sel",

				      "i2s2_src_sel",

				      "i2s3_src_sel",

				      "i2s0_src_div",

				      "i2s1_src_div",

				      "i2s2_src_div",

				      "i2s3_src_div",

				      "i2s0_mclk_en",

				      "i2s1_mclk_en",

				      "i2s2_mclk_en",

				      "i2s3_mclk_en",

				      "i2so0_hop_ck",

				      "i2so1_hop_ck",

				      "i2so2_hop_ck",

				      "i2so3_hop_ck",

				      "i2si0_hop_ck",

				      "i2si1_hop_ck",

				      "i2si2_hop_ck",

				      "i2si3_hop_ck",

				      "asrc0_out_ck",

				      "asrc1_out_ck",

				      "asrc2_out_ck",

				      "asrc3_out_ck",

				      "audio_afe_pd",

				      "audio_afe_conn_pd",

				      "audio_a1sys_pd",

				      "audio_a2sys_pd",

				      "audio_mrgif_pd";



			assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,

					  <&topckgen CLK_TOP_AUD_MUX2_SEL>,

					  <&topckgen CLK_TOP_AUD_MUX1_DIV>,

					  <&topckgen CLK_TOP_AUD_MUX2_DIV>;

			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,

						 <&topckgen CLK_TOP_AUD2PLL_90M>;

			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;

		};

	};

sound/soc/codecs/mc13783.c

+3 −6
Original line number Diff line number Diff line
@@ -610,6 +610,9 @@ static int mc13783_probe(struct snd_soc_codec *codec) 
{

	struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);



	snd_soc_codec_init_regmap(codec,

				  dev_get_regmap(codec->dev->parent, NULL));



	/* these are the reset values */

	mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893);

	mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX1, 0x00d35A);
@@ -728,15 +731,9 @@ static struct snd_soc_dai_driver mc13783_dai_sync[] = { 
	}

};



static struct regmap *mc13783_get_regmap(struct device *dev)

{

	return dev_get_regmap(dev->parent, NULL);

}



static const struct snd_soc_codec_driver soc_codec_dev_mc13783 = {

	.probe		= mc13783_probe,

	.remove		= mc13783_remove,

	.get_regmap	= mc13783_get_regmap,

	.component_driver = {

		.controls		= mc13783_control_list,

		.num_controls		= ARRAY_SIZE(mc13783_control_list),

sound/soc/codecs/msm8916-wcd-analog.c

+2 −6
Original line number Diff line number Diff line
@@ -712,6 +712,8 @@ static int pm8916_wcd_analog_probe(struct snd_soc_codec *codec) 
		return err;

	}



	snd_soc_codec_init_regmap(codec,

				  dev_get_regmap(codec->dev->parent, NULL));

	snd_soc_codec_set_drvdata(codec, priv);

	priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1);

	priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE);
@@ -943,11 +945,6 @@ static int pm8916_wcd_analog_set_jack(struct snd_soc_codec *codec, 
	return 0;

}



static struct regmap *pm8916_get_regmap(struct device *dev)

{

	return dev_get_regmap(dev->parent, NULL);

}



static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)

{

	struct pm8916_wcd_analog_priv *priv = arg;
@@ -1082,7 +1079,6 @@ static const struct snd_soc_codec_driver pm8916_wcd_analog = { 
	.probe = pm8916_wcd_analog_probe,

	.remove = pm8916_wcd_analog_remove,

	.set_jack = pm8916_wcd_analog_set_jack,

	.get_regmap = pm8916_get_regmap,

	.component_driver = {

		.controls = pm8916_wcd_analog_snd_controls,

		.num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),

sound/soc/codecs/nau8540.c

+80 −18
Original line number Diff line number Diff line
@@ -233,6 +233,41 @@ static SOC_ENUM_SINGLE_DECL( 
static const struct snd_kcontrol_new digital_ch1_mux =

	SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum);



static int adc_power_control(struct snd_soc_dapm_widget *w,

		struct snd_kcontrol *k, int  event)

{

	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);

	struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);



	if (SND_SOC_DAPM_EVENT_ON(event)) {

		msleep(300);

		/* DO12 and DO34 pad output enable */

		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,

			NAU8540_I2S_DO12_TRI, 0);

		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,

			NAU8540_I2S_DO34_TRI, 0);

	} else if (SND_SOC_DAPM_EVENT_OFF(event)) {

		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,

			NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);

		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,

			NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);

	}

	return 0;

}



static int aiftx_power_control(struct snd_soc_dapm_widget *w,

		struct snd_kcontrol *k, int  event)

{

	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);

	struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);



	if (SND_SOC_DAPM_EVENT_OFF(event)) {

		regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);

		regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);

	}

	return 0;

}



static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {

	SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),

	SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
@@ -247,14 +282,18 @@ static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = { 
	SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0),

	SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0),



	SND_SOC_DAPM_ADC("ADC1", NULL,

		NAU8540_REG_POWER_MANAGEMENT, 0, 0),

	SND_SOC_DAPM_ADC("ADC2", NULL,

		NAU8540_REG_POWER_MANAGEMENT, 1, 0),

	SND_SOC_DAPM_ADC("ADC3", NULL,

		NAU8540_REG_POWER_MANAGEMENT, 2, 0),

	SND_SOC_DAPM_ADC("ADC4", NULL,

		NAU8540_REG_POWER_MANAGEMENT, 3, 0),

	SND_SOC_DAPM_ADC_E("ADC1", NULL,

		NAU8540_REG_POWER_MANAGEMENT, 0, 0, adc_power_control,

		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),

	SND_SOC_DAPM_ADC_E("ADC2", NULL,

		NAU8540_REG_POWER_MANAGEMENT, 1, 0, adc_power_control,

		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),

	SND_SOC_DAPM_ADC_E("ADC3", NULL,

		NAU8540_REG_POWER_MANAGEMENT, 2, 0, adc_power_control,

		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),

	SND_SOC_DAPM_ADC_E("ADC4", NULL,

		NAU8540_REG_POWER_MANAGEMENT, 3, 0, adc_power_control,

		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),



	SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),

	SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
@@ -270,7 +309,8 @@ static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = { 
	SND_SOC_DAPM_MUX("Digital CH1 Mux",

		SND_SOC_NOPM, 0, 0, &digital_ch1_mux),



	SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0),

	SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,

		aiftx_power_control, SND_SOC_DAPM_POST_PMD),

};



static const struct snd_soc_dapm_route nau8540_dapm_routes[] = {
@@ -575,7 +615,8 @@ static void nau8540_fll_apply(struct regmap *regmap, 
		NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK,

		NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);

	regmap_update_bits(regmap, NAU8540_REG_FLL1,

		NAU8540_FLL_RATIO_MASK, fll_param->ratio);

		NAU8540_FLL_RATIO_MASK | NAU8540_ICTRL_LATCH_MASK,

		fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));

	/* FLL 16-bit fractional input */

	regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);

	/* FLL 10-bit integer input */
@@ -596,13 +637,14 @@ static void nau8540_fll_apply(struct regmap *regmap, 
			NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |

			NAU8540_FLL_FTR_SW_FILTER);

		regmap_update_bits(regmap, NAU8540_REG_FLL6,

			NAU8540_SDM_EN, NAU8540_SDM_EN);

			NAU8540_SDM_EN | NAU8540_CUTOFF500,

			NAU8540_SDM_EN | NAU8540_CUTOFF500);

	} else {

		regmap_update_bits(regmap, NAU8540_REG_FLL5,

			NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |

			NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU);

		regmap_update_bits(regmap,

			NAU8540_REG_FLL6, NAU8540_SDM_EN, 0);

		regmap_update_bits(regmap, NAU8540_REG_FLL6,

			NAU8540_SDM_EN | NAU8540_CUTOFF500, 0);

	}

}
@@ -617,17 +659,22 @@ static int nau8540_set_pll(struct snd_soc_codec *codec, int pll_id, int source, 
	switch (pll_id) {

	case NAU8540_CLK_FLL_MCLK:

		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,

			NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_MCLK);

			NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,

			NAU8540_FLL_CLK_SRC_MCLK | 0);

		break;



	case NAU8540_CLK_FLL_BLK:

		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,

			NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_BLK);

			NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,

			NAU8540_FLL_CLK_SRC_BLK |

			(0xf << NAU8540_GAIN_ERR_SFT));

		break;



	case NAU8540_CLK_FLL_FS:

		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,

			NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_FS);

			NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,

			NAU8540_FLL_CLK_SRC_FS |

			(0xf << NAU8540_GAIN_ERR_SFT));

		break;



	default:
@@ -710,9 +757,24 @@ static void nau8540_init_regs(struct nau8540 *nau8540) 
	regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,

		NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN,

		NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN);

	/* ADC OSR selection, CLK_ADC = Fs * OSR */

	/* ADC OSR selection, CLK_ADC = Fs * OSR;

	 * Channel time alignment enable.

	 */

	regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE,

		NAU8540_ADC_OSR_MASK, NAU8540_ADC_OSR_64);

		NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK,

		NAU8540_CH_SYNC | NAU8540_ADC_OSR_64);

	/* PGA input mode selection */

	regmap_update_bits(regmap, NAU8540_REG_FEPGA1,

		NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT,

		NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT);

	regmap_update_bits(regmap, NAU8540_REG_FEPGA2,

		NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT,

		NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT);

	/* DO12 and DO34 pad output disable */

	regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL1,

		NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);

	regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL2,

		NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);

}



static int __maybe_unused nau8540_suspend(struct snd_soc_codec *codec)

sound/soc/codecs/nau8540.h

+20 −0
Original line number Diff line number Diff line
@@ -100,9 +100,13 @@ 
#define NAU8540_CLK_MCLK_SRC_MASK	0xf



/* FLL1 (0x04) */

#define NAU8540_ICTRL_LATCH_SFT	10

#define NAU8540_ICTRL_LATCH_MASK	(0x7 << NAU8540_ICTRL_LATCH_SFT)

#define NAU8540_FLL_RATIO_MASK	0x7f



/* FLL3 (0x06) */

#define NAU8540_GAIN_ERR_SFT		12

#define NAU8540_GAIN_ERR_MASK		(0xf << NAU8540_GAIN_ERR_SFT)

#define NAU8540_FLL_CLK_SRC_SFT	10

#define NAU8540_FLL_CLK_SRC_MASK	(0x3 << NAU8540_FLL_CLK_SRC_SFT)

#define NAU8540_FLL_CLK_SRC_MCLK	(0 << NAU8540_FLL_CLK_SRC_SFT)
@@ -127,6 +131,7 @@ 
/* FLL6 (0x9) */

#define NAU8540_DCO_EN			(0x1 << 15)

#define NAU8540_SDM_EN			(0x1 << 14)

#define NAU8540_CUTOFF500		(0x1 << 13)



/* PCM_CTRL0 (0x10) */

#define NAU8540_I2S_BP_SFT		7
@@ -146,6 +151,7 @@ 
#define NAU8540_I2S_DF_PCM_AB		0x3



/* PCM_CTRL1 (0x11) */

#define NAU8540_I2S_DO12_TRI		(0x1 << 15)

#define NAU8540_I2S_LRC_DIV_SFT	12

#define NAU8540_I2S_LRC_DIV_MASK	(0x3 << NAU8540_I2S_LRC_DIV_SFT)

#define NAU8540_I2S_DO12_OE		(0x1 << 4)
@@ -156,6 +162,7 @@ 
#define NAU8540_I2S_BLK_DIV_MASK	0x7



/* PCM_CTRL1 (0x12) */

#define NAU8540_I2S_DO34_TRI		(0x1 << 15)

#define NAU8540_I2S_DO34_OE		(0x1 << 11)

#define NAU8540_I2S_TSLOT_L_MASK	0x3ff
@@ -165,6 +172,7 @@ 
#define NAU8540_TDM_TX_MASK		0xf



/* ADC_SAMPLE_RATE (0x3A) */

#define NAU8540_CH_SYNC		(0x1 << 14)

#define NAU8540_ADC_OSR_MASK		0x3

#define NAU8540_ADC_OSR_256		0x3

#define NAU8540_ADC_OSR_128		0x2
@@ -183,6 +191,18 @@ 
#define NAU8540_PRECHARGE_DIS		(0x1 << 13)

#define NAU8540_GLOBAL_BIAS_EN	(0x1 << 12)



/* FEPGA1 (0x69) */

#define NAU8540_FEPGA1_MODCH2_SHT_SFT	7

#define NAU8540_FEPGA1_MODCH2_SHT	(0x1 << NAU8540_FEPGA1_MODCH2_SHT_SFT)

#define NAU8540_FEPGA1_MODCH1_SHT_SFT	3

#define NAU8540_FEPGA1_MODCH1_SHT	(0x1 << NAU8540_FEPGA1_MODCH1_SHT_SFT)



/* FEPGA2 (0x6A) */

#define NAU8540_FEPGA2_MODCH4_SHT_SFT	7

#define NAU8540_FEPGA2_MODCH4_SHT	(0x1 << NAU8540_FEPGA2_MODCH4_SHT_SFT)

#define NAU8540_FEPGA2_MODCH3_SHT_SFT	3

#define NAU8540_FEPGA2_MODCH3_SHT	(0x1 << NAU8540_FEPGA2_MODCH3_SHT_SFT)





/* System Clock Source */

enum {