Commit 310f134e authored by Brijesh Singh's avatar Brijesh Singh Committed by Borislav Petkov
Browse files

x86/sev: Add defines for GHCB version 2 MSR protocol requests 

Add the necessary defines for supporting the GHCB version 2 protocol.
This includes defines for:

	- MSR-based AP hlt request/response
	- Hypervisor Feature request/response

This is the bare minimum of requests that need to be supported by a GHCB
version 2 implementation. There are more requests in the specification,
but those depend on Secure Nested Paging support being available.

These defines are shared between SEV host and guest support.

  [ bp: Fold in https://lkml.kernel.org/r/20210622144825.27588-2-joro@8bytes.org

 too.
        Simplify the brewing macro maze into readability. ]

Co-developed-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: default avatarBrijesh Singh <brijesh.singh@amd.com>
Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/YNLXQIZ5e1wjkshG@8bytes.org
parent be1a5408

arch/x86/include/asm/sev-common.h

+15 −1
Original line number Diff line number Diff line
@@ -9,8 +9,13 @@ 
#define __ASM_X86_SEV_COMMON_H



#define GHCB_MSR_INFO_POS		0

#define GHCB_MSR_INFO_MASK		(BIT_ULL(12) - 1)

#define GHCB_DATA_LOW			12

#define GHCB_MSR_INFO_MASK		(BIT_ULL(GHCB_DATA_LOW) - 1)



#define GHCB_DATA(v)			\

	(((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW)



/* SEV Information Request/Response */

#define GHCB_MSR_SEV_INFO_RESP		0x001

#define GHCB_MSR_SEV_INFO_REQ		0x002

#define GHCB_MSR_VER_MAX_POS		48
@@ -28,6 +33,7 @@ 
#define GHCB_MSR_PROTO_MAX(v)		(((v) >> GHCB_MSR_VER_MAX_POS) & GHCB_MSR_VER_MAX_MASK)

#define GHCB_MSR_PROTO_MIN(v)		(((v) >> GHCB_MSR_VER_MIN_POS) & GHCB_MSR_VER_MIN_MASK)



/* CPUID Request/Response */

#define GHCB_MSR_CPUID_REQ		0x004

#define GHCB_MSR_CPUID_RESP		0x005

#define GHCB_MSR_CPUID_FUNC_POS		32
@@ -45,6 +51,14 @@ 
		(((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \

		(((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS))



/* AP Reset Hold */

#define GHCB_MSR_AP_RESET_HOLD_REQ		0x006

#define GHCB_MSR_AP_RESET_HOLD_RESP		0x007



/* GHCB Hypervisor Feature Request/Response */

#define GHCB_MSR_HV_FT_REQ			0x080

#define GHCB_MSR_HV_FT_RESP			0x081



#define GHCB_MSR_TERM_REQ		0x100

#define GHCB_MSR_TERM_REASON_SET_POS	12

#define GHCB_MSR_TERM_REASON_SET_MASK	0xf