Unverified Commit 3103e9ef authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!7324 net: stmmac: xgmac: fix handling of DPP safety error for DMA channels 

Merge Pull Request from: @ci-robot 
 
PR sync from: Guo Mengqi <guomengqi3@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/VXQSQRNG6HXUTTGD3N4ZA34AFV6LSQAQ/ 
 
https://gitee.com/src-openeuler/kernel/issues/I9DNZK 
 
Link:https://gitee.com/openeuler/kernel/pulls/7324

 

Reviewed-by: default avatarYue Haibing <yuehaibing@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 45ef1ebc 52abc724

drivers/net/ethernet/stmicro/stmmac/common.h

+1 −0
Original line number Diff line number Diff line
@@ -189,6 +189,7 @@ struct stmmac_safety_stats { 
	unsigned long mac_errors[32];

	unsigned long mtl_errors[32];

	unsigned long dma_errors[32];

	unsigned long dma_dpp_errors[32];

};



/* Number of fields in Safety Stats */

drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

+3 −0
Original line number Diff line number Diff line
@@ -282,6 +282,8 @@ 
#define XGMAC_RXCEIE			BIT(4)

#define XGMAC_TXCEIE			BIT(0)

#define XGMAC_MTL_ECC_INT_STATUS	0x000010cc

#define XGMAC_MTL_DPP_CONTROL		0x000010e0

#define XGMAC_DDPP_DISABLE		BIT(0)

#define XGMAC_MTL_TXQ_OPMODE(x)		(0x00001100 + (0x80 * (x)))

#define XGMAC_TQS			GENMASK(25, 16)

#define XGMAC_TQS_SHIFT			16
@@ -364,6 +366,7 @@ 
#define XGMAC_DCEIE			BIT(1)

#define XGMAC_TCEIE			BIT(0)

#define XGMAC_DMA_ECC_INT_STATUS	0x0000306c

#define XGMAC_DMA_DPP_INT_STATUS	0x00003074

#define XGMAC_DMA_CH_CONTROL(x)		(0x00003100 + (0x80 * (x)))

#define XGMAC_SPH			BIT(24)

#define XGMAC_PBLx8			BIT(16)

drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c

+57 −1
Original line number Diff line number Diff line
@@ -788,6 +788,44 @@ static const struct dwxgmac3_error_desc dwxgmac3_dma_errors[32]= { 
	{ false, "UNKNOWN", "Unknown Error" }, /* 31 */

};



#define DPP_RX_ERR "Read Rx Descriptor Parity checker Error"

#define DPP_TX_ERR "Read Tx Descriptor Parity checker Error"



static const struct dwxgmac3_error_desc dwxgmac3_dma_dpp_errors[32] = {

	{ true, "TDPES0", DPP_TX_ERR },

	{ true, "TDPES1", DPP_TX_ERR },

	{ true, "TDPES2", DPP_TX_ERR },

	{ true, "TDPES3", DPP_TX_ERR },

	{ true, "TDPES4", DPP_TX_ERR },

	{ true, "TDPES5", DPP_TX_ERR },

	{ true, "TDPES6", DPP_TX_ERR },

	{ true, "TDPES7", DPP_TX_ERR },

	{ true, "TDPES8", DPP_TX_ERR },

	{ true, "TDPES9", DPP_TX_ERR },

	{ true, "TDPES10", DPP_TX_ERR },

	{ true, "TDPES11", DPP_TX_ERR },

	{ true, "TDPES12", DPP_TX_ERR },

	{ true, "TDPES13", DPP_TX_ERR },

	{ true, "TDPES14", DPP_TX_ERR },

	{ true, "TDPES15", DPP_TX_ERR },

	{ true, "RDPES0", DPP_RX_ERR },

	{ true, "RDPES1", DPP_RX_ERR },

	{ true, "RDPES2", DPP_RX_ERR },

	{ true, "RDPES3", DPP_RX_ERR },

	{ true, "RDPES4", DPP_RX_ERR },

	{ true, "RDPES5", DPP_RX_ERR },

	{ true, "RDPES6", DPP_RX_ERR },

	{ true, "RDPES7", DPP_RX_ERR },

	{ true, "RDPES8", DPP_RX_ERR },

	{ true, "RDPES9", DPP_RX_ERR },

	{ true, "RDPES10", DPP_RX_ERR },

	{ true, "RDPES11", DPP_RX_ERR },

	{ true, "RDPES12", DPP_RX_ERR },

	{ true, "RDPES13", DPP_RX_ERR },

	{ true, "RDPES14", DPP_RX_ERR },

	{ true, "RDPES15", DPP_RX_ERR },

};



static void dwxgmac3_handle_dma_err(struct net_device *ndev,

				    void __iomem *ioaddr, bool correctable,

				    struct stmmac_safety_stats *stats)
@@ -799,6 +837,13 @@ static void dwxgmac3_handle_dma_err(struct net_device *ndev, 


	dwxgmac3_log_error(ndev, value, correctable, "DMA",

			   dwxgmac3_dma_errors, STAT_OFF(dma_errors), stats);



	value = readl(ioaddr + XGMAC_DMA_DPP_INT_STATUS);

	writel(value, ioaddr + XGMAC_DMA_DPP_INT_STATUS);



	dwxgmac3_log_error(ndev, value, false, "DMA_DPP",

			   dwxgmac3_dma_dpp_errors,

			   STAT_OFF(dma_dpp_errors), stats);

}



static int dwxgmac3_safety_feat_config(void __iomem *ioaddr, unsigned int asp)
@@ -835,6 +880,12 @@ static int dwxgmac3_safety_feat_config(void __iomem *ioaddr, unsigned int asp) 
	value |= XGMAC_TMOUTEN; /* FSM Timeout Feature */

	writel(value, ioaddr + XGMAC_MAC_FSM_CONTROL);



	/* 5. Enable Data Path Parity Protection */

	value = readl(ioaddr + XGMAC_MTL_DPP_CONTROL);

	/* already enabled by default, explicit enable it again */

	value &= ~XGMAC_DDPP_DISABLE;

	writel(value, ioaddr + XGMAC_MTL_DPP_CONTROL);



	return 0;

}
@@ -868,7 +919,11 @@ static int dwxgmac3_safety_feat_irq_status(struct net_device *ndev, 
		ret |= !corr;

	}



	err = dma & (XGMAC_DEUIS | XGMAC_DECIS);

	/* DMA_DPP_Interrupt_Status is indicated by MCSIS bit in

	 * DMA_Safety_Interrupt_Status, so we handle DMA Data Path

	 * Parity Errors here

	 */

	err = dma & (XGMAC_DEUIS | XGMAC_DECIS | XGMAC_MCSIS);

	corr = dma & XGMAC_DECIS;

	if (err) {

		dwxgmac3_handle_dma_err(ndev, ioaddr, corr, stats);
@@ -884,6 +939,7 @@ static const struct dwxgmac3_error { 
	{ dwxgmac3_mac_errors },

	{ dwxgmac3_mtl_errors },

	{ dwxgmac3_dma_errors },

	{ dwxgmac3_dma_dpp_errors },

};



static int dwxgmac3_safety_feat_dump(struct stmmac_safety_stats *stats,