Commit 30f55f3f authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

drm/msm/a6xx: Move CX GMU power counter enablement to hw_init 



Since the introduction of A6xx support, we've been enabling the CX GMU
power counter 0 in a bit of a weird spot. Move it to hw_init so that
GMU wrapper GPUs can reuse the same code paths. As a bonus, this order
makes it easier to compare mainline and downstream register access traces.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542765/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent df5bb404

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+0 −6
Original line number Diff line number Diff line
@@ -479,12 +479,6 @@ static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 


	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);



	/* Set up CX GMU counter 0 to count busy ticks */

	gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);

	gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20);



	/* Enable the power counter */

	gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);

	return 0;

}

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+7 −0
Original line number Diff line number Diff line
@@ -1256,6 +1256,13 @@ static int hw_init(struct msm_gpu *gpu) 
			0x3f0243f0);

	}



	/* Set up the CX GMU counter 0 to count busy ticks */

	gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);



	/* Enable the power counter */

	gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5));

	gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);



	/* Protect registers from the CP */

	a6xx_set_cp_protect(gpu);