Commit 30bb078a authored by Nick Forrington's avatar Nick Forrington Committed by Arnaldo Carvalho de Melo
Browse files

perf vendors events arm64: Arm Cortex-X1 

Add PMU events for Arm Cortex-X1
Update mapfile.csv

Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-x1.json

which is based on PMU event descriptions from the Arm Cortex-X1 Technical
Reference Manual.

Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json



which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.

Reviewed-by: default avatarJohn Garry <john.garry@huawei.com>
Signed-off-by: default avatarNick Forrington <nick.forrington@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Andrew Kilroy <andrew.kilroy@arm.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20220520181455.340344-12-nick.forrington@arm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent cceb5f97

tools/perf/pmu-events/arch/arm64/arm/cortex-x1/branch.json

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+17 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "BR_MIS_PRED"

    },

    {

        "ArchStdEvent": "BR_PRED"

    },

    {

        "ArchStdEvent": "BR_IMMED_SPEC"

    },

    {

        "ArchStdEvent": "BR_RETURN_SPEC"

    },

    {

        "ArchStdEvent": "BR_INDIRECT_SPEC"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-x1/bus.json

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+20 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "CPU_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS"

    },

    {

        "ArchStdEvent": "BUS_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_RD"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_WR"

    },

    {

        "ArchStdEvent": "CNT_CYCLES"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-x1/cache.json

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+155 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "L1I_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1I_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L1D_CACHE"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L1I_CACHE"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L2D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB"

    },

    {

        "ArchStdEvent": "L2D_CACHE_ALLOCATE"

    },

    {

        "ArchStdEvent": "L1D_TLB"

    },

    {

        "ArchStdEvent": "L1I_TLB"

    },

    {

        "ArchStdEvent": "L3D_CACHE_ALLOCATE"

    },

    {

        "ArchStdEvent": "L3D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "L3D_CACHE"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "L2D_TLB"

    },

    {

        "ArchStdEvent": "DTLB_WALK"

    },

    {

        "ArchStdEvent": "ITLB_WALK"

    },

    {

        "ArchStdEvent": "LL_CACHE_RD"

    },

    {

        "ArchStdEvent": "LL_CACHE_MISS_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_LMISS_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_INNER"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "L1D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_RD"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_WR"

    },

    {

        "ArchStdEvent": "L1D_TLB_RD"

    },

    {

        "ArchStdEvent": "L1D_TLB_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "L2D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL_RD"

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL_WR"

    },

    {

        "ArchStdEvent": "L2D_TLB_RD"

    },

    {

        "ArchStdEvent": "L2D_TLB_WR"

    },

    {

        "ArchStdEvent": "L3D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L1I_CACHE_LMISS"

    },

    {

        "ArchStdEvent": "L2D_CACHE_LMISS_RD"

    },

    {

        "ArchStdEvent": "L3D_CACHE_LMISS_RD"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-x1/exception.json

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+47 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "EXC_TAKEN"

    },

    {

        "ArchStdEvent": "MEMORY_ERROR"

    },

    {

        "ArchStdEvent": "EXC_UNDEF"

    },

    {

        "ArchStdEvent": "EXC_SVC"

    },

    {

        "ArchStdEvent": "EXC_PABORT"

    },

    {

        "ArchStdEvent": "EXC_DABORT"

    },

    {

        "ArchStdEvent": "EXC_IRQ"

    },

    {

        "ArchStdEvent": "EXC_FIQ"

    },

    {

        "ArchStdEvent": "EXC_SMC"

    },

    {

        "ArchStdEvent": "EXC_HVC"

    },

    {

        "ArchStdEvent": "EXC_TRAP_PABORT"

    },

    {

        "ArchStdEvent": "EXC_TRAP_DABORT"

    },

    {

        "ArchStdEvent": "EXC_TRAP_OTHER"

    },

    {

        "ArchStdEvent": "EXC_TRAP_IRQ"

    },

    {

        "ArchStdEvent": "EXC_TRAP_FIQ"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-x1/instruction.json

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+80 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "SW_INCR"

    },

    {

        "ArchStdEvent": "INST_RETIRED"

    },

    {

        "ArchStdEvent": "EXC_RETURN"

    },

    {

        "ArchStdEvent": "CID_WRITE_RETIRED"

    },

    {

        "ArchStdEvent": "INST_SPEC"

    },

    {

        "ArchStdEvent": "TTBR_WRITE_RETIRED"

    },

    {

        "ArchStdEvent": "BR_RETIRED"

    },

    {

        "ArchStdEvent": "BR_MIS_PRED_RETIRED"

    },

    {

        "ArchStdEvent": "OP_RETIRED"

    },

    {

        "ArchStdEvent": "OP_SPEC"

    },

    {

        "ArchStdEvent": "LDREX_SPEC"

    },

    {

        "ArchStdEvent": "STREX_PASS_SPEC"

    },

    {

        "ArchStdEvent": "STREX_FAIL_SPEC"

    },

    {

        "ArchStdEvent": "STREX_SPEC"

    },

    {

        "ArchStdEvent": "LD_SPEC"

    },

    {

        "ArchStdEvent": "ST_SPEC"

    },

    {

        "ArchStdEvent": "DP_SPEC"

    },

    {

        "ArchStdEvent": "ASE_SPEC"

    },

    {

        "ArchStdEvent": "VFP_SPEC"

    },

    {

        "ArchStdEvent": "PC_WRITE_SPEC"

    },

    {

        "ArchStdEvent": "CRYPTO_SPEC"

    },

    {

        "ArchStdEvent": "ISB_SPEC"

    },

    {

        "ArchStdEvent": "DSB_SPEC"

    },

    {

        "ArchStdEvent": "DMB_SPEC"

    },

    {

        "ArchStdEvent": "RC_LD_SPEC"

    },

    {

        "ArchStdEvent": "RC_ST_SPEC"

    }

]