Commit 30813656 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-fix-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 

Pull dmaengine fixes from Vinod Koul:

 - HAS_IOMEM fixes for fsl edma and intel idma

 - return-value fix, interrupt vector setting and typo fix for xilinx
   xdma

 - email updates for codeaurora email domain move

 - correct pause status for pl330 driver

 - idxd clear flag on disable fix

 - function documentation fix for owl dma

 - potential un-allocated memory fix for mcf driver

* tag 'dmaengine-fix-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine:
  dmaengine: xilinx: xdma: Fix typo
  dmaengine: xilinx: xdma: Fix interrupt vector setting
  dmaengine: owl-dma: Modify mismatched function name
  dmaengine: idxd: Clear PRS disable flag when disabling IDXD device
  dmaengine: pl330: Return DMA_PAUSED when transaction is paused
  dmaengine: qcom_hidma: Update codeaurora email domain
  dmaengine: mcf-edma: Fix a potential un-allocated memory access
  dmaengine: xilinx: xdma: Fix Judgment of the return value
  idmaengine: make FSL_EDMA and INTEL_IDMA64 depends on HAS_IOMEM
parents 374a7f47 422dbc66

Documentation/ABI/testing/sysfs-platform-hidma

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ What: /sys/devices/platform/hidma-*/chid 
		/sys/devices/platform/QCOM8061:*/chid

Date:		Dec 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@codeaurora.org>"

Contact:	"Sinan Kaya <okaya@kernel.org>"

Description:

		Contains the ID of the channel within the HIDMA instance.

		It is used to associate a given HIDMA channel with the

Documentation/ABI/testing/sysfs-platform-hidma-mgmt

+10 −10
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ What: /sys/devices/platform/hidma-mgmt*/chanops/chan*/priority 
		/sys/devices/platform/QCOM8060:*/chanops/chan*/priority

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@codeaurora.org>"

Contact:	"Sinan Kaya <okaya@kernel.org>"

Description:

		Contains either 0 or 1 and indicates if the DMA channel is a

		low priority (0) or high priority (1) channel.
@@ -11,7 +11,7 @@ What: /sys/devices/platform/hidma-mgmt*/chanops/chan*/weight 
		/sys/devices/platform/QCOM8060:*/chanops/chan*/weight

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@codeaurora.org>"

Contact:	"Sinan Kaya <okaya@kernel.org>"

Description:

		Contains 0..15 and indicates the weight of the channel among

		equal priority channels during round robin scheduling.
@@ -20,7 +20,7 @@ What: /sys/devices/platform/hidma-mgmt*/chreset_timeout_cycles 
		/sys/devices/platform/QCOM8060:*/chreset_timeout_cycles

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@codeaurora.org>"

Contact:	"Sinan Kaya <okaya@kernel.org>"

Description:

		Contains the platform specific cycle value to wait after a

		reset command is issued. If the value is chosen too short,
@@ -32,7 +32,7 @@ What: /sys/devices/platform/hidma-mgmt*/dma_channels 
		/sys/devices/platform/QCOM8060:*/dma_channels

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@codeaurora.org>"

Contact:	"Sinan Kaya <okaya@kernel.org>"

Description:

		Contains the number of dma channels supported by one instance

		of HIDMA hardware. The value may change from chip to chip.
@@ -41,7 +41,7 @@ What: /sys/devices/platform/hidma-mgmt*/hw_version_major 
		/sys/devices/platform/QCOM8060:*/hw_version_major

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@codeaurora.org>"

Contact:	"Sinan Kaya <okaya@kernel.org>"

Description:

		Version number major for the hardware.
@@ -49,7 +49,7 @@ What: /sys/devices/platform/hidma-mgmt*/hw_version_minor 
		/sys/devices/platform/QCOM8060:*/hw_version_minor

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@codeaurora.org>"

Contact:	"Sinan Kaya <okaya@kernel.org>"

Description:

		Version number minor for the hardware.
@@ -57,7 +57,7 @@ What: /sys/devices/platform/hidma-mgmt*/max_rd_xactions 
		/sys/devices/platform/QCOM8060:*/max_rd_xactions

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@codeaurora.org>"

Contact:	"Sinan Kaya <okaya@kernel.org>"

Description:

		Contains a value between 0 and 31. Maximum number of

		read transactions that can be issued back to back.
@@ -69,7 +69,7 @@ What: /sys/devices/platform/hidma-mgmt*/max_read_request 
		/sys/devices/platform/QCOM8060:*/max_read_request

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@codeaurora.org>"

Contact:	"Sinan Kaya <okaya@kernel.org>"

Description:

		Size of each read request. The value needs to be a power

		of two and can be between 128 and 1024.
@@ -78,7 +78,7 @@ What: /sys/devices/platform/hidma-mgmt*/max_wr_xactions 
		/sys/devices/platform/QCOM8060:*/max_wr_xactions

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@codeaurora.org>"

Contact:	"Sinan Kaya <okaya@kernel.org>"

Description:

		Contains a value between 0 and 31. Maximum number of

		write transactions that can be issued back to back.
@@ -91,7 +91,7 @@ What: /sys/devices/platform/hidma-mgmt*/max_write_request 
		/sys/devices/platform/QCOM8060:*/max_write_request

Date:		Nov 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@codeaurora.org>"

Contact:	"Sinan Kaya <okaya@kernel.org>"

Description:

		Size of each write request. The value needs to be a power

		of two and can be between 128 and 1024.

drivers/dma/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -211,6 +211,7 @@ config FSL_DMA 
config FSL_EDMA

	tristate "Freescale eDMA engine support"

	depends on OF

	depends on HAS_IOMEM

	select DMA_ENGINE

	select DMA_VIRTUAL_CHANNELS

	help
@@ -280,6 +281,7 @@ config IMX_SDMA 


config INTEL_IDMA64

	tristate "Intel integrated DMA 64-bit support"

	depends on HAS_IOMEM

	select DMA_ENGINE

	select DMA_VIRTUAL_CHANNELS

	help

drivers/dma/idxd/device.c

+1 −3
Original line number Diff line number Diff line
@@ -384,9 +384,7 @@ static void idxd_wq_disable_cleanup(struct idxd_wq *wq) 
	wq->threshold = 0;

	wq->priority = 0;

	wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;

	clear_bit(WQ_FLAG_DEDICATED, &wq->flags);

	clear_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags);

	clear_bit(WQ_FLAG_ATS_DISABLE, &wq->flags);

	wq->flags = 0;

	memset(wq->name, 0, WQ_NAME_SIZE);

	wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;

	idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH);

drivers/dma/mcf-edma.c

+7 −6
Original line number Diff line number Diff line
@@ -190,7 +190,13 @@ static int mcf_edma_probe(struct platform_device *pdev) 
		return -EINVAL;

	}



	if (!pdata->dma_channels) {

		dev_info(&pdev->dev, "setting default channel number to 64");

		chans = 64;

	} else {

		chans = pdata->dma_channels;

	}



	len = sizeof(*mcf_edma) + sizeof(*mcf_chan) * chans;

	mcf_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);

	if (!mcf_edma)
@@ -202,11 +208,6 @@ static int mcf_edma_probe(struct platform_device *pdev) 
	mcf_edma->drvdata = &mcf_data;

	mcf_edma->big_endian = 1;



	if (!mcf_edma->n_chans) {

		dev_info(&pdev->dev, "setting default channel number to 64");

		mcf_edma->n_chans = 64;

	}



	mutex_init(&mcf_edma->fsl_edma_mutex);



	mcf_edma->membase = devm_platform_ioremap_resource(pdev, 0);