Commit 3076e09f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-next-20221109' of git://linuxtv.org/pinchartl/media into drm-next 



- Renesas RZ/G2L DSI support
- Renesas DU Kconfig cleanup
- Xilinx DPSUB fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Y2u+mhkPJQ4de3q5@pendragon.ideasonboard.com
parents c02f20d3 cec9e59c

Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/G2L MIPI DSI Encoder



maintainers:

  - Biju Das <biju.das.jz@bp.renesas.com>



description: |

  This binding describes the MIPI DSI encoder embedded in the Renesas

  RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with

  up to four data lanes.



allOf:

  - $ref: /schemas/display/dsi-controller.yaml#



properties:

  compatible:

    items:

      - enum:

          - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}

      - const: renesas,rzg2l-mipi-dsi



  reg:

    maxItems: 1



  interrupts:

    items:

      - description: Sequence operation channel 0 interrupt

      - description: Sequence operation channel 1 interrupt

      - description: Video-Input operation channel 1 interrupt

      - description: DSI Packet Receive interrupt

      - description: DSI Fatal Error interrupt

      - description: DSI D-PHY PPI interrupt

      - description: Debug interrupt



  interrupt-names:

    items:

      - const: seq0

      - const: seq1

      - const: vin1

      - const: rcv

      - const: ferr

      - const: ppi

      - const: debug



  clocks:

    items:

      - description: DSI D-PHY PLL multiplied clock

      - description: DSI D-PHY system clock

      - description: DSI AXI bus clock

      - description: DSI Register access clock

      - description: DSI Video clock

      - description: DSI D-PHY Escape mode transmit clock



  clock-names:

    items:

      - const: pllclk

      - const: sysclk

      - const: aclk

      - const: pclk

      - const: vclk

      - const: lpclk



  resets:

    items:

      - description: MIPI_DSI_CMN_RSTB

      - description: MIPI_DSI_ARESET_N

      - description: MIPI_DSI_PRESET_N



  reset-names:

    items:

      - const: rst

      - const: arst

      - const: prst



  power-domains:

    maxItems: 1



  ports:

    $ref: /schemas/graph.yaml#/properties/ports



    properties:

      port@0:

        $ref: /schemas/graph.yaml#/properties/port

        description: Parallel input port



      port@1:

        $ref: /schemas/graph.yaml#/$defs/port-base

        unevaluatedProperties: false

        description: DSI output port



        properties:

          endpoint:

            $ref: /schemas/media/video-interfaces.yaml#

            unevaluatedProperties: false



            properties:

              data-lanes:

                description: array of physical DSI data lane indexes.

                minItems: 1

                items:

                  - const: 1

                  - const: 2

                  - const: 3

                  - const: 4



            required:

              - data-lanes



    required:

      - port@0

      - port@1



required:

  - compatible

  - reg

  - interrupts

  - interrupt-names

  - clocks

  - clock-names

  - resets

  - reset-names

  - power-domains

  - ports



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/r9a07g044-cpg.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    dsi0: dsi@10850000 {

        compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";

        reg = <0x10850000 0x20000>;

        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-names = "seq0", "seq1", "vin1", "rcv",

                          "ferr", "ppi", "debug";

        clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,

                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,

                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,

                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,

                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,

                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;

        clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";

        resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,

                 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,

                 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;

        reset-names = "rst", "arst", "prst";

        power-domains = <&cpg>;



        ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@0 {

                reg = <0>;

                dsi0_in: endpoint {

                    remote-endpoint = <&du_out_dsi0>;

                };

            };



            port@1 {

                reg = <1>;

                dsi0_out: endpoint {

                    data-lanes = <1 2 3 4>;

                    remote-endpoint = <&adv7535_in>;

                };

            };

        };

    };

...

drivers/gpu/drm/rcar-du/Kconfig

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@@ -41,8 +41,6 @@ config DRM_RCAR_LVDS 
	depends on DRM_RCAR_USE_LVDS

	select DRM_KMS_HELPER

	select DRM_PANEL

	select OF_FLATTREE

	select OF_OVERLAY



config DRM_RCAR_MIPI_DSI

	tristate "R-Car DU MIPI DSI Encoder Support"
@@ -51,6 +49,14 @@ config DRM_RCAR_MIPI_DSI 
	help

	  Enable support for the R-Car Display Unit embedded MIPI DSI encoders.



config DRM_RZG2L_MIPI_DSI

	tristate "RZ/G2L MIPI DSI Encoder Support"

	depends on DRM_BRIDGE && OF

	depends on ARCH_RENESAS || COMPILE_TEST

	select DRM_MIPI_DSI

	help

	  Enable support for the RZ/G2L Display Unit embedded MIPI DSI encoders.



config DRM_RCAR_VSP

	bool "R-Car DU VSP Compositor Support" if ARM

	default y if ARM64

drivers/gpu/drm/rcar-du/Makefile

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@@ -14,3 +14,5 @@ obj-$(CONFIG_DRM_RCAR_DU) += rcar-du-drm.o 
obj-$(CONFIG_DRM_RCAR_DW_HDMI)		+= rcar_dw_hdmi.o

obj-$(CONFIG_DRM_RCAR_LVDS)		+= rcar_lvds.o

obj-$(CONFIG_DRM_RCAR_MIPI_DSI)		+= rcar_mipi_dsi.o



obj-$(CONFIG_DRM_RZG2L_MIPI_DSI)	+= rzg2l_mipi_dsi.o

drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c

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File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h

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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * RZ/G2L MIPI DSI Interface Registers Definitions

 *

 * Copyright (C) 2022 Renesas Electronics Corporation

 */



#ifndef __RZG2L_MIPI_DSI_REGS_H__

#define __RZG2L_MIPI_DSI_REGS_H__



#include <linux/bits.h>



/* DPHY Registers */

#define DSIDPHYCTRL0			0x00

#define DSIDPHYCTRL0_CAL_EN_HSRX_OFS	BIT(16)

#define DSIDPHYCTRL0_CMN_MASTER_EN	BIT(8)

#define DSIDPHYCTRL0_RE_VDD_DETVCCQLV18	BIT(2)

#define DSIDPHYCTRL0_EN_LDO1200		BIT(1)

#define DSIDPHYCTRL0_EN_BGR		BIT(0)



#define DSIDPHYTIM0			0x04

#define DSIDPHYTIM0_TCLK_MISS(x)	((x) << 24)

#define DSIDPHYTIM0_T_INIT(x)		((x) << 0)



#define DSIDPHYTIM1			0x08

#define DSIDPHYTIM1_THS_PREPARE(x)	((x) << 24)

#define DSIDPHYTIM1_TCLK_PREPARE(x)	((x) << 16)

#define DSIDPHYTIM1_THS_SETTLE(x)	((x) << 8)

#define DSIDPHYTIM1_TCLK_SETTLE(x)	((x) << 0)



#define DSIDPHYTIM2			0x0c

#define DSIDPHYTIM2_TCLK_TRAIL(x)	((x) << 24)

#define DSIDPHYTIM2_TCLK_POST(x)	((x) << 16)

#define DSIDPHYTIM2_TCLK_PRE(x)		((x) << 8)

#define DSIDPHYTIM2_TCLK_ZERO(x)	((x) << 0)



#define DSIDPHYTIM3			0x10

#define DSIDPHYTIM3_TLPX(x)		((x) << 24)

#define DSIDPHYTIM3_THS_EXIT(x)		((x) << 16)

#define DSIDPHYTIM3_THS_TRAIL(x)	((x) << 8)

#define DSIDPHYTIM3_THS_ZERO(x)		((x) << 0)



/* --------------------------------------------------------*/

/* Link Registers */

#define LINK_REG_OFFSET			0x10000



/* Link Status Register */

#define LINKSR				0x10

#define LINKSR_LPBUSY			BIT(13)

#define LINKSR_HSBUSY			BIT(12)

#define LINKSR_VICHRUN1			BIT(8)

#define LINKSR_SQCHRUN1			BIT(4)

#define LINKSR_SQCHRUN0			BIT(0)



/* Tx Set Register */

#define TXSETR				0x100

#define TXSETR_NUMLANECAP		(0x3 << 16)

#define TXSETR_DLEN			(1 << 9)

#define TXSETR_CLEN			(1 << 8)

#define TXSETR_NUMLANEUSE(x)		(((x) & 0x3) << 0)



/* HS Clock Set Register */

#define HSCLKSETR			0x104

#define HSCLKSETR_HSCLKMODE_CONT	(1 << 1)

#define HSCLKSETR_HSCLKMODE_NON_CONT	(0 << 1)

#define HSCLKSETR_HSCLKRUN_HS		(1 << 0)

#define HSCLKSETR_HSCLKRUN_LP		(0 << 0)



/* Reset Control Register */

#define RSTCR				0x110

#define RSTCR_SWRST			BIT(0)

#define RSTCR_FCETXSTP			BIT(16)



/* Reset Status Register */

#define RSTSR				0x114

#define RSTSR_DL0DIR			(1 << 15)

#define RSTSR_DLSTPST			(0xf << 8)

#define RSTSR_SWRSTV1			(1 << 4)

#define RSTSR_SWRSTIB			(1 << 3)

#define RSTSR_SWRSTAPB			(1 << 2)

#define RSTSR_SWRSTLP			(1 << 1)

#define RSTSR_SWRSTHS			(1 << 0)



/* Clock Lane Stop Time Set Register */

#define CLSTPTSETR			0x314

#define CLSTPTSETR_CLKKPT(x)		((x) << 24)

#define CLSTPTSETR_CLKBFHT(x)		((x) << 16)

#define CLSTPTSETR_CLKSTPT(x)		((x) << 2)



/* LP Transition Time Set Register */

#define LPTRNSTSETR			0x318

#define LPTRNSTSETR_GOLPBKT(x)		((x) << 0)



/* Physical Lane Status Register */

#define PLSR				0x320

#define PLSR_CLHS2LP			BIT(27)

#define PLSR_CLLP2HS			BIT(26)



/* Video-Input Channel 1 Set 0 Register */

#define VICH1SET0R			0x400

#define VICH1SET0R_VSEN			BIT(12)

#define VICH1SET0R_HFPNOLP		BIT(10)

#define VICH1SET0R_HBPNOLP		BIT(9)

#define VICH1SET0R_HSANOLP		BIT(8)

#define VICH1SET0R_VSTPAFT		BIT(1)

#define VICH1SET0R_VSTART		BIT(0)



/* Video-Input Channel 1 Set 1 Register */

#define VICH1SET1R			0x404

#define VICH1SET1R_DLY(x)		(((x) & 0xfff) << 2)



/* Video-Input Channel 1 Status Register */

#define VICH1SR				0x410

#define VICH1SR_VIRDY			BIT(3)

#define VICH1SR_RUNNING			BIT(2)

#define VICH1SR_STOP			BIT(1)

#define VICH1SR_START			BIT(0)



/* Video-Input Channel 1 Pixel Packet Set Register */

#define VICH1PPSETR			0x420

#define VICH1PPSETR_DT_RGB18		(0x1e << 16)

#define VICH1PPSETR_DT_RGB18_LS		(0x2e << 16)

#define VICH1PPSETR_DT_RGB24		(0x3e << 16)

#define VICH1PPSETR_TXESYNC_PULSE	(1 << 15)

#define VICH1PPSETR_VC(x)		((x) << 22)



/* Video-Input Channel 1 Vertical Size Set Register */

#define VICH1VSSETR			0x428

#define VICH1VSSETR_VACTIVE(x)		(((x) & 0x7fff) << 16)

#define VICH1VSSETR_VSPOL_LOW		(1 << 15)

#define VICH1VSSETR_VSPOL_HIGH		(0 << 15)

#define VICH1VSSETR_VSA(x)		(((x) & 0xfff) << 0)



/* Video-Input Channel 1 Vertical Porch Set Register */

#define VICH1VPSETR			0x42c

#define VICH1VPSETR_VFP(x)		(((x) & 0x1fff) << 16)

#define VICH1VPSETR_VBP(x)		(((x) & 0x1fff) << 0)



/* Video-Input Channel 1 Horizontal Size Set Register */

#define VICH1HSSETR			0x430

#define VICH1HSSETR_HACTIVE(x)		(((x) & 0x7fff) << 16)

#define VICH1HSSETR_HSPOL_LOW		(1 << 15)

#define VICH1HSSETR_HSPOL_HIGH		(0 << 15)

#define VICH1HSSETR_HSA(x)		(((x) & 0xfff) << 0)



/* Video-Input Channel 1 Horizontal Porch Set Register */

#define VICH1HPSETR			0x434

#define VICH1HPSETR_HFP(x)		(((x) & 0x1fff) << 16)

#define VICH1HPSETR_HBP(x)		(((x) & 0x1fff) << 0)



#endif /* __RZG2L_MIPI_DSI_REGS_H__ */