Commit 306e3e91 authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/intel: Add event constraint for CYCLE_ACTIVITY.STALLS_MEM_ANY 



The event CYCLE_ACTIVITY.STALLS_MEM_ANY (0x14a3) should be available on
all 8 GP counters on ICL, but it's only scheduled on the first four
counters due to the current ICL constraint table.

Add a line for the CYCLE_ACTIVITY.STALLS_MEM_ANY event in the ICL
constraint table.
Correct the comments for the CYCLE_ACTIVITY.CYCLES_MEM_ANY event.

Fixes: 60176089 ("perf/x86/intel: Add Icelake support")
Reported-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20201019164529.32154-1-kan.liang@linux.intel.com
parent 43bc103a

arch/x86/events/intel/core.c

+2 −1
Original line number Diff line number Diff line
@@ -257,7 +257,8 @@ static struct event_constraint intel_icl_event_constraints[] = { 
	INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf),

	INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),

	INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff),  /* CYCLE_ACTIVITY.STALLS_TOTAL */

	INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff),  /* CYCLE_ACTIVITY.STALLS_MEM_ANY */

	INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff),  /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */

	INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff),  /* CYCLE_ACTIVITY.STALLS_MEM_ANY */

	INTEL_EVENT_CONSTRAINT(0xa3, 0xf),      /* CYCLE_ACTIVITY.* */

	INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),

	INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),