Commit 3050e4e2 authored by Fancy Fang's avatar Fancy Fang Committed by Shawn Guo
Browse files

ARM: dts: imx7ulp: remove mipi pll clock node 



According to the IMX7ULP reference manual, the mipi pll
clock comes from the MIPI PHY PLL output. So it should
not be defined as a fixed clock. So remove this clock
node and all the references to it.

Signed-off-by: default avatarFancy Fang <chen.fang@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 502d161f

arch/arm/boot/dts/imx7ulp.dtsi

+4 −13
Original line number Diff line number Diff line
@@ -87,13 +87,6 @@ 
		#clock-cells = <0>;

	};



	mpll: clock-mpll {

		compatible = "fixed-clock";

		clock-frequency = <480000000>;

		clock-output-names = "mpll";

		#clock-cells = <0>;

	};



	ahbbridge0: bus@40000000 {

		compatible = "simple-bus";

		#address-cells = <1>;
@@ -258,9 +251,9 @@ 
			compatible = "fsl,imx7ulp-scg1";

			reg = <0x403e0000 0x10000>;

			clocks = <&rosc>, <&sosc>, <&sirc>,

				 <&firc>, <&upll>, <&mpll>;

				 <&firc>, <&upll>;

			clock-names = "rosc", "sosc", "sirc",

				      "firc", "upll", "mpll";

				      "firc", "upll";

			#clock-cells = <1>;

		};
@@ -276,13 +269,12 @@ 
				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,

				 <&scg1 IMX7ULP_CLK_UPLL>,

				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,

				 <&scg1 IMX7ULP_CLK_MIPI_PLL>,

				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,

				 <&scg1 IMX7ULP_CLK_ROSC>,

				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;

			clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",

				      "apll_pfd2", "apll_pfd1", "apll_pfd0",

				      "upll", "sosc_bus_clk", "mpll",

				      "upll", "sosc_bus_clk",

				      "firc_bus_clk", "rosc", "spll_bus_clk";

			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;

			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
@@ -309,13 +301,12 @@ 
				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,

				 <&scg1 IMX7ULP_CLK_UPLL>,

				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,

				 <&scg1 IMX7ULP_CLK_MIPI_PLL>,

				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,

				 <&scg1 IMX7ULP_CLK_ROSC>,

				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;

			clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",

				      "apll_pfd2", "apll_pfd1", "apll_pfd0",

				      "upll", "sosc_bus_clk", "mpll",

				      "upll", "sosc_bus_clk",

				      "firc_bus_clk", "rosc", "spll_bus_clk";

		};

	};