Commit 303f3fe1 authored by Steffen Trumtrar's avatar Steffen Trumtrar Committed by Alexandre Torgue
Browse files

ARM: dts: stm32: Add alternate pinmux for ethernet for stm32mp15 



Add another option for the ethernet0 pins.
It is almost identical to ethernet0_rgmii_pins_c apart from TXD0/1.

This is used on the Phycore STM32MP1.

Signed-off-by: default avatarSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: default avatarAlexandre Torgue <alexandre.torgue@foss.st.com>
parent 7a5f349e

arch/arm/boot/dts/stm32mp15-pinctrl.dtsi

+50 −0
Original line number Diff line number Diff line
@@ -341,6 +341,56 @@ 
		};

	};



	ethernet0_rgmii_pins_d: rgmii-3 {

		pins1 {

			pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */

				 <STM32_PINMUX('G', 13, AF11)>,	/* ETH_RGMII_TXD0 */

				 <STM32_PINMUX('G', 14, AF11)>,	/* ETH_RGMII_TXD1 */

				 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */

				 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */

				 <STM32_PINMUX('B', 11, AF11)>,	/* ETH_RGMII_TX_CTL */

				 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */

			bias-disable;

			drive-push-pull;

			slew-rate = <2>;

		};

		pins2 {

			pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */

			bias-disable;

			drive-push-pull;

			slew-rate = <0>;

		};

		pins3 {

			pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */

				 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */

				 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */

				 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */

				 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */

				 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */

			bias-disable;

		};

	};



	ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 {

		pins1 {

			pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */

				 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */

				 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */

				 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */

				 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */

				 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */

				 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */

				 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */

				 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */

				 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */

				 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */

				 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */

				 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */

				 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */

				 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */

		};

	};



	ethernet0_rmii_pins_a: rmii-0 {

		pins1 {

			pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */