Commit 2fcc19b3 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/aspm' 

  - Use Latency Tolerance Reporting if already enabled by platform (Bjorn
    Helgaas)

  - Save/restore LTR info for suspend/resume (Bjorn Helgaas)

* pci/aspm:
  PCI/ASPM: Save LTR Capability for suspend/resume
  PCI/ASPM: Use LTR if already enabled by platform
parents 9d8e0e4b dbbfadf2

drivers/pci/pci.c

+51 −2
Original line number Diff line number Diff line
@@ -1233,7 +1233,6 @@ static void pci_restore_pcie_state(struct pci_dev *dev) 
	pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);

}





static int pci_save_pcix_state(struct pci_dev *dev)

{

	int pos;
@@ -1270,6 +1269,45 @@ static void pci_restore_pcix_state(struct pci_dev *dev) 
	pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);

}



static void pci_save_ltr_state(struct pci_dev *dev)

{

	int ltr;

	struct pci_cap_saved_state *save_state;

	u16 *cap;



	if (!pci_is_pcie(dev))

		return;



	ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);

	if (!ltr)

		return;



	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);

	if (!save_state) {

		pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");

		return;

	}



	cap = (u16 *)&save_state->cap.data[0];

	pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);

	pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);

}



static void pci_restore_ltr_state(struct pci_dev *dev)

{

	struct pci_cap_saved_state *save_state;

	int ltr;

	u16 *cap;



	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);

	ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);

	if (!save_state || !ltr)

		return;



	cap = (u16 *)&save_state->cap.data[0];

	pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);

	pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);

}



/**

 * pci_save_state - save the PCI configuration space of a device before suspending
@@ -1291,6 +1329,7 @@ int pci_save_state(struct pci_dev *dev) 
	if (i != 0)

		return i;



	pci_save_ltr_state(dev);

	pci_save_dpc_state(dev);

	return pci_save_vc_state(dev);

}
@@ -1390,7 +1429,12 @@ void pci_restore_state(struct pci_dev *dev) 
	if (!dev->state_saved)

		return;



	/* PCI Express register must be restored first */

	/*

	 * Restore max latencies (in the LTR capability) before enabling

	 * LTR itself (in the PCIe capability).

	 */

	pci_restore_ltr_state(dev);



	pci_restore_pcie_state(dev);

	pci_restore_pasid_state(dev);

	pci_restore_pri_state(dev);
@@ -2998,6 +3042,11 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev) 
	if (error)

		pci_err(dev, "unable to preallocate PCI-X save buffer\n");



	error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,

					    2 * sizeof(u16));

	if (error)

		pci_err(dev, "unable to allocate suspend buffer for LTR\n");



	pci_allocate_vc_save_buffers(dev);

}

drivers/pci/probe.c

+23 −13
Original line number Diff line number Diff line
@@ -2069,11 +2069,8 @@ static void pci_configure_ltr(struct pci_dev *dev) 
{

#ifdef CONFIG_PCIEASPM

	struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);

	u32 cap;

	struct pci_dev *bridge;



	if (!host->native_ltr)

		return;

	u32 cap, ctl;



	if (!pci_is_pcie(dev))

		return;
@@ -2082,22 +2079,35 @@ static void pci_configure_ltr(struct pci_dev *dev) 
	if (!(cap & PCI_EXP_DEVCAP2_LTR))

		return;



	/*

	 * Software must not enable LTR in an Endpoint unless the Root

	 * Complex and all intermediate Switches indicate support for LTR.

	 * PCIe r3.1, sec 6.18.

	 */

	if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)

	pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);

	if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {

		if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {

			dev->ltr_path = 1;

	else {

			return;

		}



		bridge = pci_upstream_bridge(dev);

		if (bridge && bridge->ltr_path)

			dev->ltr_path = 1;



		return;

	}



	if (dev->ltr_path)

	if (!host->native_ltr)

		return;



	/*

	 * Software must not enable LTR in an Endpoint unless the Root

	 * Complex and all intermediate Switches indicate support for LTR.

	 * PCIe r4.0, sec 6.18.

	 */

	if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||

	    ((bridge = pci_upstream_bridge(dev)) &&

	      bridge->ltr_path)) {

		pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,

					 PCI_EXP_DEVCTL2_LTR_EN);

		dev->ltr_path = 1;

	}

#endif

}