Commit 2f77da09 authored by Adam Ford's avatar Adam Ford Committed by Geert Uytterhoeven
Browse files

clk: renesas: r8a774e1: Add 3DGE and ZG support 



The 3DGE and ZG clocks are necessary to support the 3D graphics.

Signed-off-by: default avatarAdam Ford <aford173@gmail.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230617150302.38477-3-aford173@gmail.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent f7b0dfff

drivers/clk/renesas/r8a774e1-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = { 
	/* Core Clock Outputs */

	DEF_GEN3_Z("z",		R8A774E1_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),

	DEF_GEN3_Z("z2",	R8A774E1_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),

	DEF_GEN3_Z("zg",	R8A774E1_CLK_ZG,    CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),

	DEF_FIXED("ztr",        R8A774E1_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A774E1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A774E1_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -124,6 +125,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {

	DEF_MOD("3dge",			 112,	R8A774E1_CLK_ZG),

	DEF_MOD("fdp1-1",		 118,	R8A774E1_CLK_S0D1),

	DEF_MOD("fdp1-0",		 119,	R8A774E1_CLK_S0D1),

	DEF_MOD("tmu4",			 121,	R8A774E1_CLK_S0D6),