Commit 2f488884 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Changes in dc to allow full update in some cases 



Changes in dc to allow for different cases where full update is
required.

Signed-off-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8d8a6af7

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+13 −9
Original line number Diff line number Diff line
@@ -1773,10 +1773,11 @@ void dcn20_populate_dml_writeback_from_context( 
}



int dcn20_populate_dml_pipes_from_context(

		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)

		struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)

{

	int pipe_cnt, i;

	bool synchronized_vblank = true;

	struct resource_context *res_ctx = &context->res_ctx;



	for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {

		if (!res_ctx->pipe_ctx[i].stream)
@@ -1796,10 +1797,13 @@ int dcn20_populate_dml_pipes_from_context( 


	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

		struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;

		unsigned int v_total;

		int output_bpc;



		if (!res_ctx->pipe_ctx[i].stream)

			continue;



		v_total = timing->v_total;

		/* todo:

		pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;

		pipes[pipe_cnt].pipe.src.dcc = 0;
@@ -1812,7 +1816,7 @@ int dcn20_populate_dml_pipes_from_context( 
			pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;

			/* 1/2 vblank */

			pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =

				(timing->v_total - timing->v_addressable

				(v_total - timing->v_addressable

					- timing->v_border_top - timing->v_border_bottom) / 2;

			/* 36 bytes dp, 32 hdmi */

			pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
@@ -1826,13 +1830,13 @@ int dcn20_populate_dml_pipes_from_context( 
				- timing->h_addressable

				- timing->h_border_left

				- timing->h_border_right;

		pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch;

		pipes[pipe_cnt].pipe.dest.vblank_start = v_total - timing->v_front_porch;

		pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start

				- timing->v_addressable

				- timing->v_border_top

				- timing->v_border_bottom;

		pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;

		pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;

		pipes[pipe_cnt].pipe.dest.vtotal = v_total;

		pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;

		pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;

		pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
@@ -1967,8 +1971,8 @@ int dcn20_populate_dml_pipes_from_context( 
			pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;

			pipes[pipe_cnt].pipe.src.is_hsplit = 0;

			pipes[pipe_cnt].pipe.dest.odm_combine = 0;

			pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total;

			pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total;

			pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;

			pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;

		} else {

			struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;

			struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
@@ -2430,7 +2434,7 @@ bool dcn20_fast_validate_bw( 


	dcn20_merge_pipes_for_validate(dc, context);



	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, &context->res_ctx, pipes);

	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);



	*pipe_cnt_out = pipe_cnt;
@@ -2576,10 +2580,10 @@ static void dcn20_calculate_wm( 
	if (pipe_cnt != pipe_idx) {

		if (dc->res_pool->funcs->populate_dml_pipes)

			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,

				&context->res_ctx, pipes);

				context, pipes);

		else

			pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,

				&context->res_ctx, pipes);

				context, pipes);

	}



	*out_pipe_cnt = pipe_cnt;

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ unsigned int dcn20_calc_max_scaled_time( 
		enum mmhubbub_wbif_mode mode,

		unsigned int urgent_watermark);

int dcn20_populate_dml_pipes_from_context(

		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);

		struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);

struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(

		struct dc_state *state,

		const struct resource_pool *pool,

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

+6 −5
Original line number Diff line number Diff line
@@ -650,7 +650,7 @@ static const struct dcn10_stream_encoder_mask se_mask = { 
static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);



static int dcn21_populate_dml_pipes_from_context(

		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);

		struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);



static struct input_pixel_processor *dcn21_ipp_create(

	struct dc_context *ctx, uint32_t inst)
@@ -1053,10 +1053,10 @@ void dcn21_calculate_wm( 
	if (pipe_cnt != pipe_idx) {

		if (dc->res_pool->funcs->populate_dml_pipes)

			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,

				&context->res_ctx, pipes);

				context, pipes);

		else

			pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,

				&context->res_ctx, pipes);

				context, pipes);

	}



	*out_pipe_cnt = pipe_cnt;
@@ -1591,10 +1591,11 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx) 
}



static int dcn21_populate_dml_pipes_from_context(

		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)

		struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)

{

	uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, res_ctx, pipes);

	uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);

	int i;

	struct resource_context *res_ctx = &context->res_ctx;



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/inc/core_types.h

+1 −1
Original line number Diff line number Diff line
@@ -101,7 +101,7 @@ struct resource_funcs { 


	int (*populate_dml_pipes)(

		struct dc *dc,

		struct resource_context *res_ctx,

		struct dc_state *context,

		display_e2e_pipe_params_st *pipes);



	enum dc_status (*validate_global)(