Commit 2f3f9586 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: add helper to init rlc fw in header v2_0 



To initialize rlc firmware in header v2_0

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent af81a920

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c

+64 −0
Original line number Diff line number Diff line
@@ -272,3 +272,67 @@ void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev) 
			      &adev->gfx.rlc.cp_table_gpu_addr,

			      (void **)&adev->gfx.rlc.cp_table_ptr);

}



static int amdgpu_gfx_rlc_init_microcode_v2_0(struct amdgpu_device *adev)

{

	const struct common_firmware_header *common_hdr;

	const struct rlc_firmware_header_v2_0 *rlc_hdr;

	struct amdgpu_firmware_info *info;

	unsigned int *tmp;

	unsigned int i;



	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;



	adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);

	adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);

	adev->gfx.rlc.save_and_restore_offset =

		le32_to_cpu(rlc_hdr->save_and_restore_offset);

	adev->gfx.rlc.clear_state_descriptor_offset =

		le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);

	adev->gfx.rlc.avail_scratch_ram_locations =

		le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);

	adev->gfx.rlc.reg_restore_list_size =

		le32_to_cpu(rlc_hdr->reg_restore_list_size);

	adev->gfx.rlc.reg_list_format_start =

		le32_to_cpu(rlc_hdr->reg_list_format_start);

	adev->gfx.rlc.reg_list_format_separate_start =

		le32_to_cpu(rlc_hdr->reg_list_format_separate_start);

	adev->gfx.rlc.starting_offsets_start =

		le32_to_cpu(rlc_hdr->starting_offsets_start);

	adev->gfx.rlc.reg_list_format_size_bytes =

		le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);

	adev->gfx.rlc.reg_list_size_bytes =

		le32_to_cpu(rlc_hdr->reg_list_size_bytes);

	adev->gfx.rlc.register_list_format =

		kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +

			adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);

	if (!adev->gfx.rlc.register_list_format) {

		dev_err(adev->dev, "failed to allocate memory for rlc register_list_format\n");

		return -ENOMEM;

	}



	tmp = (unsigned int *)((uintptr_t)rlc_hdr +

			le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));

	for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)

		adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);



	adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;



	tmp = (unsigned int *)((uintptr_t)rlc_hdr +

			le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));

	for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)

		adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);



	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];

		info->ucode_id = AMDGPU_UCODE_ID_RLC_G;

		info->fw = adev->gfx.rlc_fw;

		if (info->fw) {

			common_hdr = (const struct common_firmware_header *)info->fw->data;

			adev->firmware.fw_size +=

				ALIGN(le32_to_cpu(common_hdr->ucode_size_bytes), PAGE_SIZE);

		}

	}



	return 0;

}