Commit 2f138c66 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

dt-bindings: clock: sm6375-gpucc: Add VDD_GX 



The GPUCC block on SM6375 is powered by VDD_CX and VDD_GX. If the latter
rail is not online, GX_GDSC will never turn on. Describe the missing
handles.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230529-topic-sm6375gpuccpd-v1-1-8d57c41a6066@linaro.org
parent e88c533d

Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml

+15 −0
Original line number Diff line number Diff line
@@ -27,9 +27,21 @@ properties: 
      - description: GPLL0 div branch source

      - description: SNoC DVM GFX source



  power-domains:

    description:

      A phandle and PM domain specifier for the VDD_GX power rail

    maxItems: 1



  required-opps:

    description:

      A phandle to an OPP node describing required VDD_GX performance point.

    maxItems: 1



required:

  - compatible

  - clocks

  - power-domains

  - required-opps



allOf:

  - $ref: qcom,gcc.yaml#
@@ -40,6 +52,7 @@ examples: 
  - |

    #include <dt-bindings/clock/qcom,sm6375-gcc.h>

    #include <dt-bindings/clock/qcom,rpmcc.h>

    #include <dt-bindings/power/qcom-rpmpd.h>



    soc {

        #address-cells = <2>;
@@ -52,6 +65,8 @@ examples: 
                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,

                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,

                     <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;

            power-domains = <&rpmpd SM6375_VDDGX>;

            required-opps = <&rpmpd_opp_low_svs>;

            #clock-cells = <1>;

            #reset-cells = <1>;

            #power-domain-cells = <1>;