Commit 2f0f6b17 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'dsa-microchip-phylink-mac-config' 



Arun Ramadoss says:

====================
net: dsa: microchip: add support for phylink mac config and link up

This patch series add support common phylink mac config and link up for the ksz
series switches. At present, ksz8795 and ksz9477 doesn't implement the phylink
mac config and link up. It configures the mac interface in the port setup hook.
ksz8830 series switch does not mac link configuration. For lan937x switches, in
the part support patch series has support only for MII and RMII configuration.
Some group of switches have some register address and bit fields common and
others are different. So, this patch aims to have common phylink implementation
which configures the register based on the chip id.

Changes in v2
- combined the modification of duplex, tx_pause and rx_pause into single
  function.

Changes in v1
- Squash the reading rgmii value from dt to patch which apply the rgmii value
- Created the new function ksz_port_set_xmii_speed
- Seperated the namespace values for xmii_ctrl_0 and xmii_ctrl_1 register
- Applied the rgmii delay value based on the rx/tx-internal-delay-ps
====================

Reviewed-by: default avatarVladimir Oltean <olteanv@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 060468f0 f3d890f5

drivers/net/dsa/microchip/ksz8795.c

+0 −40
Original line number Diff line number Diff line
@@ -26,11 +26,6 @@ 
#include "ksz8795_reg.h"

#include "ksz8.h"



static bool ksz_is_ksz88x3(struct ksz_device *dev)

{

	return dev->chip_id == 0x8830;

}



static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)

{

	regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
@@ -1116,7 +1111,6 @@ void ksz8_port_mirror_del(struct ksz_device *dev, int port, 
static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)

{

	struct ksz_port *p = &dev->ports[port];

	u8 data8;



	if (!p->interface && dev->compat_interface) {

		dev_warn(dev->dev,
@@ -1125,40 +1119,6 @@ static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port) 
			 port);

		p->interface = dev->compat_interface;

	}



	/* Configure MII interface for proper network communication. */

	ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);

	data8 &= ~PORT_INTERFACE_TYPE;

	data8 &= ~PORT_GMII_1GPS_MODE;

	switch (p->interface) {

	case PHY_INTERFACE_MODE_MII:

		p->phydev.speed = SPEED_100;

		break;

	case PHY_INTERFACE_MODE_RMII:

		data8 |= PORT_INTERFACE_RMII;

		p->phydev.speed = SPEED_100;

		break;

	case PHY_INTERFACE_MODE_GMII:

		data8 |= PORT_GMII_1GPS_MODE;

		data8 |= PORT_INTERFACE_GMII;

		p->phydev.speed = SPEED_1000;

		break;

	default:

		data8 &= ~PORT_RGMII_ID_IN_ENABLE;

		data8 &= ~PORT_RGMII_ID_OUT_ENABLE;

		if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||

		    p->interface == PHY_INTERFACE_MODE_RGMII_RXID)

			data8 |= PORT_RGMII_ID_IN_ENABLE;

		if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||

		    p->interface == PHY_INTERFACE_MODE_RGMII_TXID)

			data8 |= PORT_RGMII_ID_OUT_ENABLE;

		data8 |= PORT_GMII_1GPS_MODE;

		data8 |= PORT_INTERFACE_RGMII;

		p->phydev.speed = SPEED_1000;

		break;

	}

	ksz_write8(dev, REG_PORT_5_CTRL_6, data8);

	p->phydev.duplex = 1;

}



void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)

drivers/net/dsa/microchip/ksz8795_reg.h

+0 −8
Original line number Diff line number Diff line
@@ -170,15 +170,7 @@ 
#define REG_PORT_5_CTRL_6		0x56



#define PORT_MII_INTERNAL_CLOCK		BIT(7)

#define PORT_GMII_1GPS_MODE		BIT(6)

#define PORT_RGMII_ID_IN_ENABLE		BIT(4)

#define PORT_RGMII_ID_OUT_ENABLE	BIT(3)

#define PORT_GMII_MAC_MODE		BIT(2)

#define PORT_INTERFACE_TYPE		0x3

#define PORT_INTERFACE_MII		0

#define PORT_INTERFACE_RMII		1

#define PORT_INTERFACE_GMII		2

#define PORT_INTERFACE_RGMII		3



#define REG_PORT_1_CTRL_7		0x17

#define REG_PORT_2_CTRL_7		0x27

drivers/net/dsa/microchip/ksz9477.c

+6 −177
Original line number Diff line number Diff line
@@ -19,11 +19,6 @@ 
#include "ksz_common.h"

#include "ksz9477.h"



/* Used with variable features to indicate capabilities. */

#define GBIT_SUPPORT			BIT(0)

#define NEW_XMII			BIT(1)

#define IS_9893				BIT(2)



static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)

{

	regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
@@ -866,142 +861,18 @@ void ksz9477_port_mirror_del(struct ksz_device *dev, int port, 
			     PORT_MIRROR_SNIFFER, false);

}



static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)

{

	bool gbit;



	if (dev->features & NEW_XMII)

		gbit = !(data & PORT_MII_NOT_1GBIT);

	else

		gbit = !!(data & PORT_MII_1000MBIT_S1);

	return gbit;

}



static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)

{

	if (dev->features & NEW_XMII) {

		if (gbit)

			*data &= ~PORT_MII_NOT_1GBIT;

		else

			*data |= PORT_MII_NOT_1GBIT;

	} else {

		if (gbit)

			*data |= PORT_MII_1000MBIT_S1;

		else

			*data &= ~PORT_MII_1000MBIT_S1;

	}

}



static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)

{

	int mode;



	if (dev->features & NEW_XMII) {

		switch (data & PORT_MII_SEL_M) {

		case PORT_MII_SEL:

			mode = 0;

			break;

		case PORT_RMII_SEL:

			mode = 1;

			break;

		case PORT_GMII_SEL:

			mode = 2;

			break;

		default:

			mode = 3;

		}

	} else {

		switch (data & PORT_MII_SEL_M) {

		case PORT_MII_SEL_S1:

			mode = 0;

			break;

		case PORT_RMII_SEL_S1:

			mode = 1;

			break;

		case PORT_GMII_SEL_S1:

			mode = 2;

			break;

		default:

			mode = 3;

		}

	}

	return mode;

}



static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)

{

	u8 xmii;



	if (dev->features & NEW_XMII) {

		switch (mode) {

		case 0:

			xmii = PORT_MII_SEL;

			break;

		case 1:

			xmii = PORT_RMII_SEL;

			break;

		case 2:

			xmii = PORT_GMII_SEL;

			break;

		default:

			xmii = PORT_RGMII_SEL;

			break;

		}

	} else {

		switch (mode) {

		case 0:

			xmii = PORT_MII_SEL_S1;

			break;

		case 1:

			xmii = PORT_RMII_SEL_S1;

			break;

		case 2:

			xmii = PORT_GMII_SEL_S1;

			break;

		default:

			xmii = PORT_RGMII_SEL_S1;

			break;

		}

	}

	*data &= ~PORT_MII_SEL_M;

	*data |= xmii;

}



static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)

{

	phy_interface_t interface;

	bool gbit;

	int mode;

	u8 data8;



	if (port < dev->phy_port_cnt)

		return PHY_INTERFACE_MODE_NA;

	ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);

	gbit = ksz9477_get_gbit(dev, data8);

	mode = ksz9477_get_xmii(dev, data8);

	switch (mode) {

	case 2:

		interface = PHY_INTERFACE_MODE_GMII;

		if (gbit)

			break;

		fallthrough;

	case 0:

		interface = PHY_INTERFACE_MODE_MII;

		break;

	case 1:

		interface = PHY_INTERFACE_MODE_RMII;

		break;

	default:

		interface = PHY_INTERFACE_MODE_RGMII;

		if (data8 & PORT_RGMII_ID_EG_ENABLE)

			interface = PHY_INTERFACE_MODE_RGMII_TXID;

		if (data8 & PORT_RGMII_ID_IG_ENABLE) {

			interface = PHY_INTERFACE_MODE_RGMII_RXID;

			if (data8 & PORT_RGMII_ID_EG_ENABLE)

				interface = PHY_INTERFACE_MODE_RGMII_ID;

		}

		break;

	}



	gbit = ksz_get_gbit(dev, port);



	interface = ksz_get_xmii(dev, port, gbit);



	return interface;

}
@@ -1073,10 +944,9 @@ void ksz9477_get_caps(struct ksz_device *dev, int port, 


void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)

{

	struct ksz_port *p = &dev->ports[port];

	struct dsa_switch *ds = dev->ds;

	u8 data8, member;

	u16 data16;

	u8 member;



	/* enable tag tail for host port */

	if (cpu_port)
@@ -1116,44 +986,6 @@ void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 
		ksz_port_cfg(dev, port, REG_PORT_CTRL_0,

			     PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,

			     true);



		/* configure MAC to 1G & RGMII mode */

		ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);

		switch (p->interface) {

		case PHY_INTERFACE_MODE_MII:

			ksz9477_set_xmii(dev, 0, &data8);

			ksz9477_set_gbit(dev, false, &data8);

			p->phydev.speed = SPEED_100;

			break;

		case PHY_INTERFACE_MODE_RMII:

			ksz9477_set_xmii(dev, 1, &data8);

			ksz9477_set_gbit(dev, false, &data8);

			p->phydev.speed = SPEED_100;

			break;

		case PHY_INTERFACE_MODE_GMII:

			ksz9477_set_xmii(dev, 2, &data8);

			ksz9477_set_gbit(dev, true, &data8);

			p->phydev.speed = SPEED_1000;

			break;

		default:

			ksz9477_set_xmii(dev, 3, &data8);

			ksz9477_set_gbit(dev, true, &data8);

			data8 &= ~PORT_RGMII_ID_IG_ENABLE;

			data8 &= ~PORT_RGMII_ID_EG_ENABLE;

			if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||

			    p->interface == PHY_INTERFACE_MODE_RGMII_RXID)

				data8 |= PORT_RGMII_ID_IG_ENABLE;

			if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||

			    p->interface == PHY_INTERFACE_MODE_RGMII_TXID)

				data8 |= PORT_RGMII_ID_EG_ENABLE;

			/* On KSZ9893, disable RGMII in-band status support */

			if (dev->features & IS_9893)

				data8 &= ~PORT_MII_MAC_MODE;

			p->phydev.speed = SPEED_1000;

			break;

		}

		ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);

		p->phydev.duplex = 1;

	}



	if (cpu_port)
@@ -1341,9 +1173,6 @@ int ksz9477_switch_init(struct ksz_device *dev) 
			dev->features &= ~GBIT_SUPPORT;

		dev->phy_port_cnt = 2;

	} else {

		/* Chip uses new XMII register definitions. */

		dev->features |= NEW_XMII;



		/* Chip does not support gigabit. */

		if (!(data8 & SW_GIGABIT_ABLE))

			dev->features &= ~GBIT_SUPPORT;

drivers/net/dsa/microchip/ksz9477_reg.h

+0 −24
Original line number Diff line number Diff line
@@ -1175,35 +1175,11 @@ 
#define PORT_LINK_STATUS_FAIL		BIT(0)



/* 3 - xMII */

#define REG_PORT_XMII_CTRL_0		0x0300



#define PORT_SGMII_SEL			BIT(7)

#define PORT_MII_FULL_DUPLEX		BIT(6)

#define PORT_MII_100MBIT		BIT(4)

#define PORT_GRXC_ENABLE		BIT(0)



#define REG_PORT_XMII_CTRL_1		0x0301



#define PORT_RMII_CLK_SEL		BIT(7)

/* S1 */

#define PORT_MII_1000MBIT_S1		BIT(6)

/* S2 */

#define PORT_MII_NOT_1GBIT		BIT(6)

#define PORT_MII_SEL_EDGE		BIT(5)

#define PORT_RGMII_ID_IG_ENABLE		BIT(4)

#define PORT_RGMII_ID_EG_ENABLE		BIT(3)

#define PORT_MII_MAC_MODE		BIT(2)

#define PORT_MII_SEL_M			0x3

/* S1 */

#define PORT_MII_SEL_S1			0x0

#define PORT_RMII_SEL_S1		0x1

#define PORT_GMII_SEL_S1		0x2

#define PORT_RGMII_SEL_S1		0x3

/* S2 */

#define PORT_RGMII_SEL			0x0

#define PORT_RMII_SEL			0x1

#define PORT_GMII_SEL			0x2

#define PORT_MII_SEL			0x3



/* 4 - MAC */

#define REG_PORT_MAC_CTRL_0		0x0400

drivers/net/dsa/microchip/ksz_common.c

+310 −2
Original line number Diff line number Diff line
@@ -222,8 +222,7 @@ static const struct ksz_dev_ops lan937x_dev_ops = { 
	.mirror_add = ksz9477_port_mirror_add,

	.mirror_del = ksz9477_port_mirror_del,

	.get_caps = lan937x_phylink_get_caps,

	.phylink_mac_config = lan937x_phylink_mac_config,

	.phylink_mac_link_up = lan937x_phylink_mac_link_up,

	.setup_rgmii_delay = lan937x_setup_rgmii_delay,

	.fdb_dump = ksz9477_fdb_dump,

	.fdb_add = ksz9477_fdb_add,

	.fdb_del = ksz9477_fdb_del,
@@ -257,6 +256,8 @@ static const u16 ksz8795_regs[] = { 
	[S_START_CTRL]			= 0x01,

	[S_BROADCAST_CTRL]		= 0x06,

	[S_MULTICAST_CTRL]		= 0x04,

	[P_XMII_CTRL_0]			= 0x06,

	[P_XMII_CTRL_1]			= 0x56,

};



static const u32 ksz8795_masks[] = {
@@ -279,6 +280,24 @@ static const u32 ksz8795_masks[] = { 
	[DYNAMIC_MAC_TABLE_FID]		= GENMASK(26, 20),

	[DYNAMIC_MAC_TABLE_SRC_PORT]	= GENMASK(26, 24),

	[DYNAMIC_MAC_TABLE_TIMESTAMP]	= GENMASK(28, 27),

	[P_MII_TX_FLOW_CTRL]		= BIT(5),

	[P_MII_RX_FLOW_CTRL]		= BIT(5),

};



static const u8 ksz8795_xmii_ctrl0[] = {

	[P_MII_100MBIT]			= 0,

	[P_MII_10MBIT]			= 1,

	[P_MII_FULL_DUPLEX]		= 0,

	[P_MII_HALF_DUPLEX]		= 1,

};



static const u8 ksz8795_xmii_ctrl1[] = {

	[P_RGMII_SEL]			= 3,

	[P_GMII_SEL]			= 2,

	[P_RMII_SEL]			= 1,

	[P_MII_SEL]			= 0,

	[P_GMII_1GBIT]			= 1,

	[P_GMII_NOT_1GBIT]		= 0,

};



static const u8 ksz8795_shifts[] = {
@@ -351,20 +370,42 @@ static const u16 ksz9477_regs[] = { 
	[S_START_CTRL]			= 0x0300,

	[S_BROADCAST_CTRL]		= 0x0332,

	[S_MULTICAST_CTRL]		= 0x0331,

	[P_XMII_CTRL_0]			= 0x0300,

	[P_XMII_CTRL_1]			= 0x0301,

};



static const u32 ksz9477_masks[] = {

	[ALU_STAT_WRITE]		= 0,

	[ALU_STAT_READ]			= 1,

	[P_MII_TX_FLOW_CTRL]		= BIT(5),

	[P_MII_RX_FLOW_CTRL]		= BIT(3),

};



static const u8 ksz9477_shifts[] = {

	[ALU_STAT_INDEX]		= 16,

};



static const u8 ksz9477_xmii_ctrl0[] = {

	[P_MII_100MBIT]			= 1,

	[P_MII_10MBIT]			= 0,

	[P_MII_FULL_DUPLEX]		= 1,

	[P_MII_HALF_DUPLEX]		= 0,

};



static const u8 ksz9477_xmii_ctrl1[] = {

	[P_RGMII_SEL]			= 0,

	[P_RMII_SEL]			= 1,

	[P_GMII_SEL]			= 2,

	[P_MII_SEL]			= 3,

	[P_GMII_1GBIT]			= 0,

	[P_GMII_NOT_1GBIT]		= 1,

};



static const u32 lan937x_masks[] = {

	[ALU_STAT_WRITE]		= 1,

	[ALU_STAT_READ]			= 2,

	[P_MII_TX_FLOW_CTRL]		= BIT(5),

	[P_MII_RX_FLOW_CTRL]		= BIT(3),

};



static const u8 lan937x_shifts[] = {
@@ -388,6 +429,8 @@ const struct ksz_chip_data ksz_switch_chips[] = { 
		.regs = ksz8795_regs,

		.masks = ksz8795_masks,

		.shifts = ksz8795_shifts,

		.xmii_ctrl0 = ksz8795_xmii_ctrl0,

		.xmii_ctrl1 = ksz8795_xmii_ctrl1,

		.supports_mii = {false, false, false, false, true},

		.supports_rmii = {false, false, false, false, true},

		.supports_rgmii = {false, false, false, false, true},
@@ -424,6 +467,8 @@ const struct ksz_chip_data ksz_switch_chips[] = { 
		.regs = ksz8795_regs,

		.masks = ksz8795_masks,

		.shifts = ksz8795_shifts,

		.xmii_ctrl0 = ksz8795_xmii_ctrl0,

		.xmii_ctrl1 = ksz8795_xmii_ctrl1,

		.supports_mii = {false, false, false, false, true},

		.supports_rmii = {false, false, false, false, true},

		.supports_rgmii = {false, false, false, false, true},
@@ -446,6 +491,8 @@ const struct ksz_chip_data ksz_switch_chips[] = { 
		.regs = ksz8795_regs,

		.masks = ksz8795_masks,

		.shifts = ksz8795_shifts,

		.xmii_ctrl0 = ksz8795_xmii_ctrl0,

		.xmii_ctrl1 = ksz8795_xmii_ctrl1,

		.supports_mii = {false, false, false, false, true},

		.supports_rmii = {false, false, false, false, true},

		.supports_rgmii = {false, false, false, false, true},
@@ -488,6 +535,8 @@ const struct ksz_chip_data ksz_switch_chips[] = { 
		.regs = ksz9477_regs,

		.masks = ksz9477_masks,

		.shifts = ksz9477_shifts,

		.xmii_ctrl0 = ksz9477_xmii_ctrl0,

		.xmii_ctrl1 = ksz9477_xmii_ctrl1,

		.supports_mii	= {false, false, false, false,

				   false, true, false},

		.supports_rmii	= {false, false, false, false,
@@ -514,6 +563,8 @@ const struct ksz_chip_data ksz_switch_chips[] = { 
		.regs = ksz9477_regs,

		.masks = ksz9477_masks,

		.shifts = ksz9477_shifts,

		.xmii_ctrl0 = ksz9477_xmii_ctrl0,

		.xmii_ctrl1 = ksz9477_xmii_ctrl1,

		.supports_mii	= {false, false, false, false,

				   false, true, true},

		.supports_rmii	= {false, false, false, false,
@@ -539,6 +590,8 @@ const struct ksz_chip_data ksz_switch_chips[] = { 
		.regs = ksz9477_regs,

		.masks = ksz9477_masks,

		.shifts = ksz9477_shifts,

		.xmii_ctrl0 = ksz9477_xmii_ctrl0,

		.xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */

		.supports_mii = {false, false, true},

		.supports_rmii = {false, false, true},

		.supports_rgmii = {false, false, true},
@@ -561,6 +614,8 @@ const struct ksz_chip_data ksz_switch_chips[] = { 
		.regs = ksz9477_regs,

		.masks = ksz9477_masks,

		.shifts = ksz9477_shifts,

		.xmii_ctrl0 = ksz9477_xmii_ctrl0,

		.xmii_ctrl1 = ksz9477_xmii_ctrl1,

		.supports_mii	= {false, false, false, false,

				   false, true, true},

		.supports_rmii	= {false, false, false, false,
@@ -586,6 +641,8 @@ const struct ksz_chip_data ksz_switch_chips[] = { 
		.regs = ksz9477_regs,

		.masks = lan937x_masks,

		.shifts = lan937x_shifts,

		.xmii_ctrl0 = ksz9477_xmii_ctrl0,

		.xmii_ctrl1 = ksz9477_xmii_ctrl1,

		.supports_mii = {false, false, false, false, true},

		.supports_rmii = {false, false, false, false, true},

		.supports_rgmii = {false, false, false, false, true},
@@ -607,6 +664,8 @@ const struct ksz_chip_data ksz_switch_chips[] = { 
		.regs = ksz9477_regs,

		.masks = lan937x_masks,

		.shifts = lan937x_shifts,

		.xmii_ctrl0 = ksz9477_xmii_ctrl0,

		.xmii_ctrl1 = ksz9477_xmii_ctrl1,

		.supports_mii = {false, false, false, false, true, true},

		.supports_rmii = {false, false, false, false, true, true},

		.supports_rgmii = {false, false, false, false, true, true},
@@ -628,6 +687,8 @@ const struct ksz_chip_data ksz_switch_chips[] = { 
		.regs = ksz9477_regs,

		.masks = lan937x_masks,

		.shifts = lan937x_shifts,

		.xmii_ctrl0 = ksz9477_xmii_ctrl0,

		.xmii_ctrl1 = ksz9477_xmii_ctrl1,

		.supports_mii	= {false, false, false, false,

				   true, true, false, false},

		.supports_rmii	= {false, false, false, false,
@@ -653,6 +714,8 @@ const struct ksz_chip_data ksz_switch_chips[] = { 
		.regs = ksz9477_regs,

		.masks = lan937x_masks,

		.shifts = lan937x_shifts,

		.xmii_ctrl0 = ksz9477_xmii_ctrl0,

		.xmii_ctrl1 = ksz9477_xmii_ctrl1,

		.supports_mii	= {false, false, false, false,

				   true, true, false, false},

		.supports_rmii	= {false, false, false, false,
@@ -678,6 +741,8 @@ const struct ksz_chip_data ksz_switch_chips[] = { 
		.regs = ksz9477_regs,

		.masks = lan937x_masks,

		.shifts = lan937x_shifts,

		.xmii_ctrl0 = ksz9477_xmii_ctrl0,

		.xmii_ctrl1 = ksz9477_xmii_ctrl1,

		.supports_mii	= {false, false, false, false,

				   true, true, false, false},

		.supports_rmii	= {false, false, false, false,
@@ -1343,14 +1408,205 @@ static int ksz_max_mtu(struct dsa_switch *ds, int port) 
	return dev->dev_ops->max_mtu(dev, port);

}



static void ksz_set_xmii(struct ksz_device *dev, int port,

			 phy_interface_t interface)

{

	const u8 *bitval = dev->info->xmii_ctrl1;

	struct ksz_port *p = &dev->ports[port];

	const u16 *regs = dev->info->regs;

	u8 data8;



	ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);



	data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |

		   P_RGMII_ID_EG_ENABLE);



	switch (interface) {

	case PHY_INTERFACE_MODE_MII:

		data8 |= bitval[P_MII_SEL];

		break;

	case PHY_INTERFACE_MODE_RMII:

		data8 |= bitval[P_RMII_SEL];

		break;

	case PHY_INTERFACE_MODE_GMII:

		data8 |= bitval[P_GMII_SEL];

		break;

	case PHY_INTERFACE_MODE_RGMII:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII_TXID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

		data8 |= bitval[P_RGMII_SEL];

		/* On KSZ9893, disable RGMII in-band status support */

		if (dev->features & IS_9893)

			data8 &= ~P_MII_MAC_MODE;

		break;

	default:

		dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",

			phy_modes(interface), port);

		return;

	}



	if (p->rgmii_tx_val)

		data8 |= P_RGMII_ID_EG_ENABLE;



	if (p->rgmii_rx_val)

		data8 |= P_RGMII_ID_IG_ENABLE;



	/* Write the updated value */

	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);

}



phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)

{

	const u8 *bitval = dev->info->xmii_ctrl1;

	const u16 *regs = dev->info->regs;

	phy_interface_t interface;

	u8 data8;

	u8 val;



	ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);



	val = FIELD_GET(P_MII_SEL_M, data8);



	if (val == bitval[P_MII_SEL]) {

		if (gbit)

			interface = PHY_INTERFACE_MODE_GMII;

		else

			interface = PHY_INTERFACE_MODE_MII;

	} else if (val == bitval[P_RMII_SEL]) {

		interface = PHY_INTERFACE_MODE_RGMII;

	} else {

		interface = PHY_INTERFACE_MODE_RGMII;

		if (data8 & P_RGMII_ID_EG_ENABLE)

			interface = PHY_INTERFACE_MODE_RGMII_TXID;

		if (data8 & P_RGMII_ID_IG_ENABLE) {

			interface = PHY_INTERFACE_MODE_RGMII_RXID;

			if (data8 & P_RGMII_ID_EG_ENABLE)

				interface = PHY_INTERFACE_MODE_RGMII_ID;

		}

	}



	return interface;

}



static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,

				   unsigned int mode,

				   const struct phylink_link_state *state)

{

	struct ksz_device *dev = ds->priv;



	if (ksz_is_ksz88x3(dev))

		return;



	/* Internal PHYs */

	if (dev->info->internal_phy[port])

		return;



	if (phylink_autoneg_inband(mode)) {

		dev_err(dev->dev, "In-band AN not supported!\n");

		return;

	}



	ksz_set_xmii(dev, port, state->interface);



	if (dev->dev_ops->phylink_mac_config)

		dev->dev_ops->phylink_mac_config(dev, port, mode, state);



	if (dev->dev_ops->setup_rgmii_delay)

		dev->dev_ops->setup_rgmii_delay(dev, port);

}



bool ksz_get_gbit(struct ksz_device *dev, int port)

{

	const u8 *bitval = dev->info->xmii_ctrl1;

	const u16 *regs = dev->info->regs;

	bool gbit = false;

	u8 data8;

	bool val;



	ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);



	val = FIELD_GET(P_GMII_1GBIT_M, data8);



	if (val == bitval[P_GMII_1GBIT])

		gbit = true;



	return gbit;

}



static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)

{

	const u8 *bitval = dev->info->xmii_ctrl1;

	const u16 *regs = dev->info->regs;

	u8 data8;



	ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);



	data8 &= ~P_GMII_1GBIT_M;



	if (gbit)

		data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);

	else

		data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);



	/* Write the updated value */

	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);

}



static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)

{

	const u8 *bitval = dev->info->xmii_ctrl0;

	const u16 *regs = dev->info->regs;

	u8 data8;



	ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);



	data8 &= ~P_MII_100MBIT_M;



	if (speed == SPEED_100)

		data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);

	else

		data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);



	/* Write the updated value */

	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);

}



static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)

{

	if (speed == SPEED_1000)

		ksz_set_gbit(dev, port, true);

	else

		ksz_set_gbit(dev, port, false);



	if (speed == SPEED_100 || speed == SPEED_10)

		ksz_set_100_10mbit(dev, port, speed);

}



static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,

				bool tx_pause, bool rx_pause)

{

	const u8 *bitval = dev->info->xmii_ctrl0;

	const u32 *masks = dev->info->masks;

	const u16 *regs = dev->info->regs;

	u8 mask;

	u8 val;



	mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |

	       masks[P_MII_RX_FLOW_CTRL];



	if (duplex == DUPLEX_FULL)

		val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);

	else

		val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);



	if (tx_pause)

		val |= masks[P_MII_TX_FLOW_CTRL];



	if (rx_pause)

		val |= masks[P_MII_RX_FLOW_CTRL];



	ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);

}



static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
@@ -1360,6 +1616,19 @@ static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 
				    int duplex, bool tx_pause, bool rx_pause)

{

	struct ksz_device *dev = ds->priv;

	struct ksz_port *p;



	p = &dev->ports[port];



	/* Internal PHYs */

	if (dev->info->internal_phy[port])

		return;



	p->phydev.speed = speed;



	ksz_port_set_xmii_speed(dev, port, speed);



	ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);



	if (dev->dev_ops->phylink_mac_link_up)

		dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
@@ -1494,6 +1763,43 @@ struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 
}

EXPORT_SYMBOL(ksz_switch_alloc);



static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,

				  struct device_node *port_dn)

{

	phy_interface_t phy_mode = dev->ports[port_num].interface;

	int rx_delay = -1, tx_delay = -1;



	if (!phy_interface_mode_is_rgmii(phy_mode))

		return;



	of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);

	of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);



	if (rx_delay == -1 && tx_delay == -1) {

		dev_warn(dev->dev,

			 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "

			 "please update device tree to specify \"rx-internal-delay-ps\" and "

			 "\"tx-internal-delay-ps\"",

			 port_num);



		if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||

		    phy_mode == PHY_INTERFACE_MODE_RGMII_ID)

			rx_delay = 2000;



		if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||

		    phy_mode == PHY_INTERFACE_MODE_RGMII_ID)

			tx_delay = 2000;

	}



	if (rx_delay < 0)

		rx_delay = 0;

	if (tx_delay < 0)

		tx_delay = 0;



	dev->ports[port_num].rgmii_rx_val = rx_delay;

	dev->ports[port_num].rgmii_tx_val = tx_delay;

}



int ksz_switch_register(struct ksz_device *dev)

{

	const struct ksz_chip_data *info;
@@ -1591,6 +1897,8 @@ int ksz_switch_register(struct ksz_device *dev) 
				}

				of_get_phy_mode(port,

						&dev->ports[port_num].interface);



				ksz_parse_rgmii_delay(dev, port_num, port);

			}

			of_node_put(ports);

		}