Commit 2ef8e39f authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'octeontx2-af-next' 



Ratheesh Kannoth says:

====================
octeontx2: *** Exact Match Table and Field hash ***

*** Exact match table and Field hash support for CN10KB silicon ***

Ratheesh Kannoth (11):

These patch series enables exact match table in CN10KB silicon. Legacy
silicon used NPC mcam to do packet fields/channel matching for NPC rules.
NPC mcam resources exahausted as customer use case increased.
Supporting many DMAC filter becomes a challenge, as RPM based filter
count is less. Exact match table has 4way 2K entry table and a 32 entry
fully associative cam table. Second table is to handle hash
table collision overflows in 4way 2K entry table. Enabling exact match table
results in KEX key to be appended with Hit/Miss status. This can be used
to match in NPC mcam for a more generic rule and drop those packets than
having DMAC drop rules for each DMAC entry in NPC mcam.

  octeontx2-af: Exact match support
  octeontx2-af: Exact match scan from kex profile
  octeontx2-af: devlink configuration support
  octeontx2-af: FLR handler for exact match table.
  octeontx2-af: Drop rules for NPC MCAM
  octeontx2-af: Debugsfs support for exact match.
  octeontx2: Modify mbox request and response structures
  octeontx2-af: Wrapper functions for mac addr add/del/update/reset
  octeontx2-af: Invoke exact match functions if supported
  octeontx2-pf: Add support for exact match table.
  octeontx2-af: Enable Exact match flag in kex profile

Suman Ghosh (1):

CN10KB variant of CN10K series of silicons supports
a new feature where in a large protocol field
(eg 128bit IPv6 DIP) can be condensed into a small
hashed 32bit data. This saves a lot of space in MCAM key
and allows user to add more protocol fields into the filter.
A max of two such protocol data can be hashed.
This patch adds support for hashing IPv6 SIP and/or DIP.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents e7ce9fc9 7189d28e

drivers/net/ethernet/marvell/octeontx2/af/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -11,4 +11,4 @@ rvu_mbox-y := mbox.o rvu_trace.o 
rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \

		  rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \

		  rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \

		  rvu_sdp.o
 
		  rvu_sdp.o rvu_npc_hash.o

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+35 −6
Original line number Diff line number Diff line
@@ -169,9 +169,10 @@ M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 
M(CGX_FEATURES_GET,	0x21B, cgx_features_get, msg_req,		\

			       cgx_features_info_msg)			\

M(RPM_STATS,		0x21C, rpm_stats, msg_req, rpm_stats_rsp)	\

M(CGX_MAC_ADDR_RESET,	0x21D, cgx_mac_addr_reset, msg_req, msg_rsp)	\

M(CGX_MAC_ADDR_UPDATE,	0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \

M(CGX_MAC_ADDR_RESET,	0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \

							msg_rsp) \

M(CGX_MAC_ADDR_UPDATE,	0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \

						    cgx_mac_addr_update_rsp) \

M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg,  \

				 cgx_pfc_rsp)                               \

/* NPA mbox IDs (range 0x400 - 0x5FF) */				\
@@ -241,6 +242,9 @@ M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 
M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats,                     \

				   npc_mcam_get_stats_req,              \

				   npc_mcam_get_stats_rsp)              \

M(NPC_GET_SECRET_KEY, 0x6013, npc_get_secret_key,                     \

				   npc_get_secret_key_req,              \

				   npc_get_secret_key_rsp)              \

/* NIX mbox IDs (range 0x8000 - 0xFFFF) */				\

M(NIX_LF_ALLOC,		0x8000, nix_lf_alloc,				\

				 nix_lf_alloc_req, nix_lf_alloc_rsp)	\
@@ -428,6 +432,7 @@ struct get_hw_cap_rsp { 
	struct mbox_msghdr hdr;

	u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */

	u8 nix_shaping;		     /* Is shaping and coloring supported */

	u8 npc_hash_extract;	/* Is hash extract supported */

};



/* CGX mbox message formats */
@@ -451,6 +456,7 @@ struct cgx_fec_stats_rsp { 
struct cgx_mac_addr_set_or_get {

	struct mbox_msghdr hdr;

	u8 mac_addr[ETH_ALEN];

	u32 index;

};



/* Structure for requesting the operation to
@@ -466,7 +472,7 @@ struct cgx_mac_addr_add_req { 
 */

struct cgx_mac_addr_add_rsp {

	struct mbox_msghdr hdr;

	u8 index;

	u32 index;

};



/* Structure for requesting the operation to
@@ -474,7 +480,7 @@ struct cgx_mac_addr_add_rsp { 
 */

struct cgx_mac_addr_del_req {

	struct mbox_msghdr hdr;

	u8 index;

	u32 index;

};



/* Structure for response against the operation to
@@ -482,7 +488,7 @@ struct cgx_mac_addr_del_req { 
 */

struct cgx_max_dmac_entries_get_rsp {

	struct mbox_msghdr hdr;

	u8 max_dmac_filters;

	u32 max_dmac_filters;

};



struct cgx_link_user_info {
@@ -583,10 +589,20 @@ struct cgx_set_link_mode_rsp { 
	int status;

};



struct cgx_mac_addr_reset_req {

	struct mbox_msghdr hdr;

	u32 index;

};



struct cgx_mac_addr_update_req {

	struct mbox_msghdr hdr;

	u8 mac_addr[ETH_ALEN];

	u8 index;

	u32 index;

};



struct cgx_mac_addr_update_rsp {

	struct mbox_msghdr hdr;

	u32 index;

};



#define RVU_LMAC_FEAT_FC		BIT_ULL(0) /* pause frames */
@@ -1440,6 +1456,16 @@ struct npc_mcam_get_stats_rsp { 
	u8 stat_ena; /* enabled */

};



struct npc_get_secret_key_req {

	struct mbox_msghdr hdr;

	u8 intf;

};



struct npc_get_secret_key_rsp {

	struct mbox_msghdr hdr;

	u64 secret_key[3];

};



enum ptp_op {

	PTP_OP_ADJFINE = 0,

	PTP_OP_GET_CLOCK = 1,
@@ -1622,6 +1648,9 @@ enum cgx_af_status { 
	LMAC_AF_ERR_PERM_DENIED		= -1103,

	LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED       = -1104,

	LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,

	LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,

	LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,

	LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,

};



#endif /* MBOX_H */

drivers/net/ethernet/marvell/octeontx2/af/npc.h

+25 −0
Original line number Diff line number Diff line
@@ -10,6 +10,14 @@ 


#define NPC_KEX_CHAN_MASK	0xFFFULL



#define SET_KEX_LD(intf, lid, ltype, ld, cfg)	\

	rvu_write64(rvu, blkaddr,	\

		    NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)



#define SET_KEX_LDFLAGS(intf, ld, flags, cfg)	\

	rvu_write64(rvu, blkaddr,	\

		    NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg)



enum NPC_LID_E {

	NPC_LID_LA = 0,

	NPC_LID_LB,
@@ -200,6 +208,7 @@ enum key_fields { 
	NPC_ERRLEV,

	NPC_ERRCODE,

	NPC_LXMB,

	NPC_EXACT_RESULT,

	NPC_LA,

	NPC_LB,

	NPC_LC,
@@ -380,6 +389,22 @@ struct nix_rx_action { 
#endif

};



/* NPC_AF_INTFX_KEX_CFG field masks */

#define NPC_EXACT_NIBBLE_START		40

#define NPC_EXACT_NIBBLE_END		43

#define NPC_EXACT_NIBBLE		GENMASK_ULL(43, 40)



/* NPC_EXACT_KEX_S nibble definitions for each field */

#define NPC_EXACT_NIBBLE_HIT		BIT_ULL(40)

#define NPC_EXACT_NIBBLE_OPC		BIT_ULL(40)

#define NPC_EXACT_NIBBLE_WAY		BIT_ULL(40)

#define NPC_EXACT_NIBBLE_INDEX		GENMASK_ULL(43, 41)



#define NPC_EXACT_RESULT_HIT		BIT_ULL(0)

#define NPC_EXACT_RESULT_OPC		GENMASK_ULL(2, 1)

#define NPC_EXACT_RESULT_WAY		GENMASK_ULL(4, 3)

#define NPC_EXACT_RESULT_IDX		GENMASK_ULL(15, 5)



/* NPC_AF_INTFX_KEX_CFG field masks */

#define NPC_PARSE_NIBBLE		GENMASK_ULL(30, 0)

drivers/net/ethernet/marvell/octeontx2/af/npc_profile.h

+3 −2
Original line number Diff line number Diff line
@@ -155,7 +155,7 @@ 


/* Rx parse key extract nibble enable */

#define NPC_PARSE_NIBBLE_INTF_RX	(NPC_PARSE_NIBBLE_CHAN | \

					 NPC_PARSE_NIBBLE_ERRCODE | \

					 NPC_PARSE_NIBBLE_L2L3_BCAST | \

					 NPC_PARSE_NIBBLE_LA_LTYPE | \

					 NPC_PARSE_NIBBLE_LB_LTYPE | \

					 NPC_PARSE_NIBBLE_LC_LTYPE | \
@@ -15123,7 +15123,8 @@ static struct npc_mcam_kex npc_mkex_default = { 
	.kpu_version = NPC_KPU_PROFILE_VER,

	.keyx_cfg = {

		/* nibble: LA..LE (ltype only) + Error code + Channel */

		[NIX_INTF_RX] = ((u64)NPC_MCAM_KEY_X2 << 32) | NPC_PARSE_NIBBLE_INTF_RX,

		[NIX_INTF_RX] = ((u64)NPC_MCAM_KEY_X2 << 32) | NPC_PARSE_NIBBLE_INTF_RX |

						(u64)NPC_EXACT_NIBBLE_HIT,

		/* nibble: LA..LE (ltype only) */

		[NIX_INTF_TX] = ((u64)NPC_MCAM_KEY_X2 << 32) | NPC_PARSE_NIBBLE_INTF_TX,

	},

drivers/net/ethernet/marvell/octeontx2/af/rvu.c

+16 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include "ptp.h"



#include "rvu_trace.h"

#include "rvu_npc_hash.h"



#define DRV_NAME	"rvu_af"

#define DRV_STRING      "Marvell OcteonTX2 RVU Admin Function Driver"
@@ -68,6 +69,8 @@ static void rvu_setup_hw_capabilities(struct rvu *rvu) 
	hw->cap.nix_tx_link_bp = true;

	hw->cap.nix_rx_multicast = true;

	hw->cap.nix_shaper_toggle_wait = false;

	hw->cap.npc_hash_extract = false;

	hw->cap.npc_exact_match_enabled = false;

	hw->rvu = rvu;



	if (is_rvu_pre_96xx_C0(rvu)) {
@@ -85,6 +88,9 @@ static void rvu_setup_hw_capabilities(struct rvu *rvu) 


	if (!is_rvu_otx2(rvu))

		hw->cap.per_pf_mbox_regs = true;



	if (is_rvu_npc_hash_extract_en(rvu))

		hw->cap.npc_hash_extract = true;

}



/* Poll a RVU block's register 'offset', for a 'zero'
@@ -1122,6 +1128,12 @@ static int rvu_setup_hw_resources(struct rvu *rvu) 
		goto cgx_err;

	}



	err = rvu_npc_exact_init(rvu);

	if (err) {

		dev_err(rvu->dev, "failed to initialize exact match table\n");

		return err;

	}



	/* Assign MACs for CGX mapped functions */

	rvu_setup_pfvf_macaddress(rvu);
@@ -1991,6 +2003,7 @@ int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 


	rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping;

	rsp->nix_shaping = hw->cap.nix_shaping;

	rsp->npc_hash_extract = hw->cap.npc_hash_extract;



	return 0;

}
@@ -2548,6 +2561,9 @@ static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 


static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)

{

	if (rvu_npc_exact_has_match_table(rvu))

		rvu_npc_exact_reset(rvu, pcifunc);



	mutex_lock(&rvu->flr_lock);

	/* Reset order should reflect inter-block dependencies:

	 * 1. Reset any packet/work sources (NIX, CPT, TIM)