Commit 2edb79a5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2022-09-08' of... 

Merge tag 'drm-intel-fixes-2022-09-08' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- Fix MIPI sequence block copy from BIOS' table. (Ville)
- Fix PCODE min freq setup when GuC's SLPC is in use. (Rodrigo)
- Implement Workaround for eDP. (Ville)
- Fix has_flat_ccs selection for DG1. (Matt)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Yxn1WpmUJnJpqq23@intel.com
parents b34c1d53 151e0e0f

drivers/gpu/drm/i915/display/intel_bios.c

+7 −0
Original line number Diff line number Diff line
@@ -479,6 +479,13 @@ init_bdb_block(struct drm_i915_private *i915, 


	block_size = get_blocksize(block);



	/*

	 * Version number and new block size are considered

	 * part of the header for MIPI sequenece block v3+.

	 */

	if (section_id == BDB_MIPI_SEQUENCE && *(const u8 *)block >= 3)

		block_size += 5;



	entry = kzalloc(struct_size(entry, data, max(min_size, block_size) + 3),

			GFP_KERNEL);

	if (!entry) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

+22 −0
Original line number Diff line number Diff line
@@ -671,6 +671,28 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp, 
	intel_dp_compute_rate(intel_dp, crtc_state->port_clock,

			      &link_bw, &rate_select);



	/*

	 * WaEdpLinkRateDataReload

	 *

	 * Parade PS8461E MUX (used on varius TGL+ laptops) needs

	 * to snoop the link rates reported by the sink when we

	 * use LINK_RATE_SET in order to operate in jitter cleaning

	 * mode (as opposed to redriver mode). Unfortunately it

	 * loses track of the snooped link rates when powered down,

	 * so we need to make it re-snoop often. Without this high

	 * link rates are not stable.

	 */

	if (!link_bw) {

		struct intel_connector *connector = intel_dp->attached_connector;

		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];



		drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Reloading eDP link rates\n",

			    connector->base.base.id, connector->base.name);



		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,

				 sink_rates, sizeof(sink_rates));

	}



	if (link_bw)

		drm_dbg_kms(&i915->drm,

			    "[ENCODER:%d:%s] Using LINK_BW_SET value %02x\n",

drivers/gpu/drm/i915/gem/i915_gem_object.c

+3 −0
Original line number Diff line number Diff line
@@ -723,6 +723,9 @@ bool i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj) 
	bool lmem_placement = false;

	int i;



	if (!HAS_FLAT_CCS(to_i915(obj->base.dev)))

		return false;



	for (i = 0; i < obj->mm.n_placements; i++) {

		/* Compression is not allowed for the objects with smem placement */

		if (obj->mm.placements[i]->type == INTEL_MEMORY_SYSTEM)

drivers/gpu/drm/i915/gem/i915_gem_ttm.c

+1 −1
Original line number Diff line number Diff line
@@ -297,7 +297,7 @@ static struct ttm_tt *i915_ttm_tt_create(struct ttm_buffer_object *bo, 
		i915_tt->is_shmem = true;

	}



	if (HAS_FLAT_CCS(i915) && i915_gem_object_needs_ccs_pages(obj))

	if (i915_gem_object_needs_ccs_pages(obj))

		ccs_pages = DIV_ROUND_UP(DIV_ROUND_UP(bo->base.size,

						      NUM_BYTES_PER_CCS_BYTE),

					 PAGE_SIZE);

drivers/gpu/drm/i915/gt/intel_llc.c

+9 −10
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include "intel_llc.h"

#include "intel_mchbar_regs.h"

#include "intel_pcode.h"

#include "intel_rps.h"



struct ia_constants {

	unsigned int min_gpu_freq;
@@ -55,9 +56,6 @@ static bool get_ia_constants(struct intel_llc *llc, 
	if (!HAS_LLC(i915) || IS_DGFX(i915))

		return false;



	if (rps->max_freq <= rps->min_freq)

		return false;



	consts->max_ia_freq = cpu_max_MHz();



	consts->min_ring_freq =
@@ -65,13 +63,8 @@ static bool get_ia_constants(struct intel_llc *llc, 
	/* convert DDR frequency from units of 266.6MHz to bandwidth */

	consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);



	consts->min_gpu_freq = rps->min_freq;

	consts->max_gpu_freq = rps->max_freq;

	if (GRAPHICS_VER(i915) >= 9) {

		/* Convert GT frequency to 50 HZ units */

		consts->min_gpu_freq /= GEN9_FREQ_SCALER;

		consts->max_gpu_freq /= GEN9_FREQ_SCALER;

	}

	consts->min_gpu_freq = intel_rps_get_min_raw_freq(rps);

	consts->max_gpu_freq = intel_rps_get_max_raw_freq(rps);



	return true;

}
@@ -130,6 +123,12 @@ static void gen6_update_ring_freq(struct intel_llc *llc) 
	if (!get_ia_constants(llc, &consts))

		return;



	/*

	 * Although this is unlikely on any platform during initialization,

	 * let's ensure we don't get accidentally into infinite loop

	 */

	if (consts.max_gpu_freq <= consts.min_gpu_freq)

		return;

	/*

	 * For each potential GPU frequency, load a ring frequency we'd like

	 * to use for memory access.  We do this by specifying the IA frequency