Commit 2ec9bc8d authored by Robert Marko's avatar Robert Marko Committed by Vinod Koul
Browse files

phy: qcom-qmp-pcie: make pipe clock rate configurable 



IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz
like every other PCIe QMP PHY does, so make it configurable as part of the
qmp_phy_cfg.

Signed-off-by: default avatarRobert Marko <robimarko@gmail.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220621195512.1760362-1-robimarko@gmail.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent fe841d5b

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+12 −2
Original line number Diff line number Diff line
@@ -1284,6 +1284,9 @@ struct qmp_phy_cfg { 


	/* true, if PHY has secondary tx/rx lanes to be configured */

	bool is_dual_lane_phy;



	/* QMP PHY pipe clock interface rate */

	unsigned long pipe_clock_rate;

};



/**
@@ -2121,8 +2124,15 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 


	init.ops = &clk_fixed_rate_ops;



	/* controllers using QMP phys use 125MHz pipe clock interface */

	/*

	 * Controllers using QMP PHY-s use 125MHz pipe clock interface

	 * unless other frequency is specified in the PHY config.

	 */

	if (qmp->phys[0]->cfg->pipe_clock_rate)

		fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate;

	else

		fixed->fixed_rate = 125000000;



	fixed->hw.init = &init;



	ret = devm_clk_hw_register(qmp->dev, &fixed->hw);