Commit 2e99cd7a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-fixes-2021-04-02' of https://gitlab.freedesktop.org/drm/msm into drm-fixes 



some more minor fixes:
- a5xx/a6xx timestamp fix
- microcode version check
- fail path fix
- block programming fix
- error removal fix.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGsMj7Nv3vVaVWMxPy8Y=Z_SnZmVKhKgKDxDYTr9rGN_+w@mail.gmail.com
parents 2bbbb07d 12aca1ce

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+2 −2
Original line number Diff line number Diff line
@@ -1386,8 +1386,8 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu) 


static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)

{

	*value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_CP_0_LO,

		REG_A5XX_RBBM_PERFCTR_CP_0_HI);

	*value = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO,

		REG_A5XX_RBBM_ALWAYSON_COUNTER_HI);



	return 0;

}

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+12 −6
Original line number Diff line number Diff line
@@ -567,17 +567,17 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 
	}  else {

		/*

		 * a650 tier targets don't need whereami but still need to be

		 * equal to or newer than 1.95 for other security fixes

		 * equal to or newer than 0.95 for other security fixes

		 */

		if (adreno_is_a650(adreno_gpu)) {

			if ((buf[0] & 0xfff) >= 0x195) {

			if ((buf[0] & 0xfff) >= 0x095) {

				ret = true;

				goto out;

			}



			DRM_DEV_ERROR(&gpu->pdev->dev,

				"a650 SQE ucode is too old. Have version %x need at least %x\n",

				buf[0] & 0xfff, 0x195);

				buf[0] & 0xfff, 0x095);

		}



		/*
@@ -1228,8 +1228,8 @@ static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 
	/* Force the GPU power on so we can read this register */

	a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);



	*value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO,

		REG_A6XX_RBBM_PERFCTR_CP_0_HI);

	*value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,

		REG_A6XX_CP_ALWAYS_ON_COUNTER_HI);



	a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);

	mutex_unlock(&perfcounter_oob);
@@ -1406,7 +1406,13 @@ static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, 
	int ret;



	ret = nvmem_cell_read_u16(dev, "speed_bin", &speedbin);

	if (ret) {

	/*

	 * -ENOENT means that the platform doesn't support speedbin which is

	 * fine

	 */

	if (ret == -ENOENT) {

		return 0;

	} else if (ret) {

		DRM_DEV_ERROR(dev,

			      "failed to read speed-bin (%d). Some OPPs may not be supported by hardware",

			      ret);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

+3 −1
Original line number Diff line number Diff line
@@ -496,7 +496,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, 


	DPU_REG_WRITE(c, CTL_TOP, mode_sel);

	DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);

	DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0));

	if (cfg->merge_3d)

		DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,

			      BIT(cfg->merge_3d - MERGE_3D_0));

}



static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,

drivers/gpu/drm/msm/msm_drv.c

+1 −0
Original line number Diff line number Diff line
@@ -570,6 +570,7 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv) 
	kfree(priv);

err_put_drm_dev:

	drm_dev_put(ddev);

	platform_set_drvdata(pdev, NULL);

	return ret;

}