Commit 2e7fabab authored by Sumit Garg's avatar Sumit Garg Committed by Liao Chen
Browse files

irqchip/gic-v3: Enable support for SGIs to act as NMIs 

maillist inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8PLUM?from=project-issue
CVE: NA
Reference: https://lore.kernel.org/all/20201102161706.xfqdsro7q7k65ybb@gabell/



-------------------------------------------------

Add support to handle SGIs as pseudo NMIs. As SGIs or IPIs default to a
special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI
handler update in case of SGIs.

Also, enable NMI support prior to gic_smp_init() as allocation of SGIs
as IRQs/NMIs happen as part of this routine.

Signed-off-by: default avatarSumit Garg <sumit.garg@linaro.org>
Signed-off-by: default avatarWei Li <liwei391@huawei.com>
Reviewed-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
Signed-off-by: default avatarRuan Jinjie <ruanjinjie@huawei.com>
Signed-off-by: default avatarLiao Chen <liaochen4@huawei.com>
parent 41ddf73f

drivers/irqchip/irq-gic-v3.c

+21 −8
Original line number Diff line number Diff line
@@ -527,6 +527,7 @@ static u32 gic_get_ppi_index(struct irq_data *d) 
static int gic_irq_nmi_setup(struct irq_data *d)

{

	struct irq_desc *desc = irq_to_desc(d->irq);

	u32 idx;



	if (!gic_supports_nmi())

		return -EINVAL;
@@ -544,16 +545,22 @@ static int gic_irq_nmi_setup(struct irq_data *d) 
		return -EINVAL;



	/* desc lock should already be held */

	if (gic_irq_in_rdist(d)) {

		u32 idx = gic_get_ppi_index(d);

	switch (get_intid_range(d)) {

	case SGI_RANGE:

		break;

	case PPI_RANGE:

	case EPPI_RANGE:

		idx = gic_get_ppi_index(d);



		/* Setting up PPI as NMI, only switch handler for first NMI */

		if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {

			refcount_set(&ppi_nmi_refs[idx], 1);

			desc->handle_irq = handle_percpu_devid_fasteoi_nmi;

		}

	} else {

		break;

	default:

		desc->handle_irq = handle_fasteoi_nmi;

		break;

	}



	gic_irq_set_prio(d, GICD_INT_NMI_PRI);
@@ -564,6 +571,7 @@ static int gic_irq_nmi_setup(struct irq_data *d) 
static void gic_irq_nmi_teardown(struct irq_data *d)

{

	struct irq_desc *desc = irq_to_desc(d->irq);

	u32 idx;



	if (WARN_ON(!gic_supports_nmi()))

		return;
@@ -581,14 +589,20 @@ static void gic_irq_nmi_teardown(struct irq_data *d) 
		return;



	/* desc lock should already be held */

	if (gic_irq_in_rdist(d)) {

		u32 idx = gic_get_ppi_index(d);

	switch (get_intid_range(d)) {

	case SGI_RANGE:

		break;

	case PPI_RANGE:

	case EPPI_RANGE:

		idx = gic_get_ppi_index(d);



		/* Tearing down NMI, only switch handler for last NMI */

		if (refcount_dec_and_test(&ppi_nmi_refs[idx]))

			desc->handle_irq = handle_percpu_devid_irq;

	} else {

		break;

	default:

		desc->handle_irq = handle_fasteoi_irq;

		break;

	}



	gic_irq_set_prio(d, GICD_INT_DEF_PRI);
@@ -2074,6 +2088,7 @@ static int __init gic_init_bases(phys_addr_t dist_phys_base, 


	gic_dist_init();

	gic_cpu_init();

	gic_enable_nmi_support();

	gic_smp_init();

	gic_cpu_pm_init();
@@ -2086,8 +2101,6 @@ static int __init gic_init_bases(phys_addr_t dist_phys_base, 
			gicv2m_init(handle, gic_data.domain);

	}



	gic_enable_nmi_support();



	return 0;



out_free: