Commit 2e0d7d3e authored by Wolfram Sang's avatar Wolfram Sang Committed by Geert Uytterhoeven
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clk: renesas: r8a779f0: Fix SCIF parent clocks 



As serial communication requires a clean clock signal, the Serial
Communication Interfaces with FIFO (SCIF) are clocked by a clock that is
not affected by Spread Spectrum or Fractional Multiplication.

Hence change the parent clocks for the SCIF modules from the S0D12_PER
clock to the SASYNCPERD4 clock (which has the same clock rate), cfr.
R-Car S4-8 Hardware User's Manual rev. 0.81.

Fixes: 24aaff6a ("clk: renesas: cpg-mssr: Add support for R-Car S4-8")
Reported-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221103143440.46449-3-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent c258e3ab

drivers/clk/renesas/r8a779f0-cpg-mssr.c

+4 −4
Original line number Diff line number Diff line
@@ -144,10 +144,10 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { 
	DEF_MOD("msiof3",	621,	R8A779F0_CLK_MSO),

	DEF_MOD("pcie0",	624,	R8A779F0_CLK_S0D2),

	DEF_MOD("pcie1",	625,	R8A779F0_CLK_S0D2),

	DEF_MOD("scif0",	702,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif1",	703,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif3",	704,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif4",	705,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif0",	702,	R8A779F0_CLK_SASYNCPERD4),

	DEF_MOD("scif1",	703,	R8A779F0_CLK_SASYNCPERD4),

	DEF_MOD("scif3",	704,	R8A779F0_CLK_SASYNCPERD4),

	DEF_MOD("scif4",	705,	R8A779F0_CLK_SASYNCPERD4),

	DEF_MOD("sdhi0",        706,    R8A779F0_CLK_SD0),

	DEF_MOD("sys-dmac0",	709,	R8A779F0_CLK_S0D3_PER),

	DEF_MOD("sys-dmac1",	710,	R8A779F0_CLK_S0D3_PER),